The BAMBI Architecture Specification


Instruction Formats:

mask 0xFC00 0000 0x03E0 0000 0x001F 0000 0x0000 F800 0x0000 07FF
fields 31 - 26 25 - 21 20 - 16 15 - 11 10 - 0
RR OPCODE dest src1 src2 000 0000 0000
RI OPCODE dest src1 16-bit Immediate
SW OPCODE src1 src2 16-bit Immediate
SHI OPCODE dest src1 0000 0000 000 | 5-bit Imm
JALR OPCODE src1 0 0000 0000 0000 0000 0000
BAL OPCODE src1 21-bit Imm
B OPCODE 00000 21-bit Imm
MTSPR OPCODE dest src1 0000 0000 0000 0000
SYS OPCODE 0000 0000 0000 0000 0000 0000 00

RR - add, cmp, cmpu, sub, and, or, xor, sll, srl, sra
RI - addi, andi, cmpi, cmpiu, lui, lw, ori, subi, xori,
SW - sw
SHI - slli, srli, srai
JALR - jalr, rfi
BAL - blt,blt., ble, ble., bgt, bgt., bge, bge., beq, beq., bne, bne.
B -b
MTSPR - mtspr, mfspr
SYS - syscall, icci

Instructions:

OPCODE[5:2] OPCODE[1:0] = 0,0 OPCODE[1:0] = 1,0 OPCODE[1:0] = 0,1 OPCODE[1:0] = 1,1
0001 add addi - -
0011 sub subi - -
0111 cmp cmpi cmpu cmpiu
0010 and andi - -
0100 or ori - -
0101 xor xori - -
0110 sll slli - -
1110 srl srli sra srai
1000 sw lw - b
1001 - - beq. beq
1010 rfi icci bne. bne
1011 jalr - blt. blt
1100 syscall lui ble. ble
1101 mfspr - bgt. bgt
1111 mtspr - bge. bge
"." appended to branch instructions indicates "predict untaken," the default is "predict taken"

User-Level Registers

There are 32 32-bit General purpose registers, accessible by instructions executing in user and system mode.
Supervisor mode has access (through the mtspr and mfspr instructions) to an additional 32 special purpose registers.
Register 30 is implicitly set by all BAL-type instructions, in addition to rfi and jalr.
Register 29 is reserved for use by system software, meaning that user-level programmers should not use it.
Register 0 is hardcoded to the value 0x0. Its value cannot be changed.

Special Purpose Supervisor Registers

Supervisor mode has access (through mtspr and mfspr) to an additional 32 special purpose registers.
SPR(0) is used to maintain the system state (user or privileged). When it contains the value 0x1, the machine is executing in privileged state. When it contains 0x0, the machine is executing in user level state. Any other value stored in SPR(0) will result in undefined behavior.
SPR(1) (Exception Program Counter (EPC)) is used to store the address of the currently executing instruction when an exception occurs.
SPR(2) (Exception Cause Register) is used to store the cause of an exception. It may indicate more than one cause, in the unlikely event of an instruction causing an exception occurs at the same time as an external interrupt.
SPR(3) (Memory Exception Address (MEA)) is used to store the address of an illegal memory reference, which can be caused by the load and store instructions.
SPR(4) (Exception Mask Register) is used to mask those exceptions which should be ignored. The only types of exceptions which can be ignored are: arithmetic exceptions and external interrupts. A bit that is set to 1 indicates that the corresponding exception is enabled, 0 indicates that the exception is disabled.
SPR(5) (Base Address Register) - explained in the Address Translation section of the architecture guide.
SPR(6) (Base Mask Register) - explained in the Address Translation section of the architecture guide.


User Level Registers Special Purpose Registers
r0 == 0x0 r16 mr0 (1-bit privileged/non-privileged state) mr16
r1 (SP) r17 mr1 (Exception PC) mr17 (undefined)
r2 r18 mr2 (Exception Cause) mr18 (undefined)
r3 r19 mr3 (Memory Exception Address (MEA)) mr19 (undefined)
r4 r20 mr4 (Exception Mask) mr20 (undefined)
r5 r21 mr5 (Base Address Reg) mr21 (undefined)
r6 r22 mr6 (Base Mask Reg) mr22 (undefined)
r7 r23 mr7 (undefined) mr23 (undefined)
r8 r24 mr8 (undefined) mr24 (undefined)
r9 r25 mr9 (undefined) mr25 (undefined)
r10 r26 mr10 (undefined) mr26 (undefined)
r11 r27 mr11 (undefined) mr27 (undefined)
r12 r28 mr12 (undefined) mr28 (undefined)
r13 r29 (Reserved for use by System Software) mr13 (undefined) mr29 (undefined)
r14 r30 (LR) mr14 (undefined) mr30 (undefined)
r15 r31 (FP) mr15 (undefined) mr31 (undefined)

Exception Handling

The BAMBI architecture defines a set of exceptional conditions which will cause the flow of execution to be transferred to a system exception handler at address 0x???. When an exceptional event occurs, the value 0x1 is placed in SPR(0), indicating that the processor is operating in privileged mode. The PC of the currently executing instruction is moved to system register SPR(1). SPR(2) is set to identify the cause of the exception, based on the exception types below. In the event of an invalid memory reference exception, System register SPR(3) is set to the address of the invalid memory reference.
Exception Cause Contents of Exception Cause Register
Arithmetic Overflow 0x1
System Call 0x2
Invalid Instruction 0x4
Invalid Memory Reference 0x8
Privilege Violation0x10
SPART Interrupt0x20
Timer Interrupt0x40

Address Translation

All addresses, generated by instruction references and load/store instructions, are 32-bit virtual addresses, which are translated into a 22-bit physical address. This translation is performed by taking the logical AND of the virtual address with the Base Mask Register (SPR 6), to mask off the upper n bits of the virtual address. The Base Address Register (SPR 5) is logically ANDed with the complement of the Base Mask Register, to mask off the lower n bits of the Base Address Register. So, the upper bits of the physical address are taken from the base address register, and the lower bits from the virtual address. This can be efficiently implemented by using the Base Mask Register and its complement to control two sets of tri-state buffers, one set whose input is the virtual address, the other set whose input is the Base Address Register.

Setting of the Base Address Register and Base Mask register are controlled by the operating system. The instruction mask register is treated as if it contains all zeros when executing in privileged mode, meaning that for all operating system references, the virtual address will be the same as the physical address.

Tools

Gnu Assembler
Gnu Compiler
ThumperOS, Mem Controller, SPART
bambi support for gcc-2.95.2 and binutils-2.9.1



Last modified: Sat May 12 17:13:52 CDT 2001