Welcome to the RISC‑V Graphical Datapath Simulator! This is a 32‑bit, single-cycle implementation of RISC‑V. All the 32-bit integer instructions are supported except the syscall and concurrency related instructions and auipc. The datapath is closely based on the design described in Computer Organization and Design RISC‑V Edition

You can write RISC‑V assembly and set the initial registers and initial data memory, and then step through the demo. You can input registers and memory as hex, unsigned decimal or signed decimal by using the dropdowns. While the demo is running, you can use the side pane to view the current memory and registers and labels show the values on each wire. Most components and wires also have a tooltip which gives more details on their functionality and current value.

You can view the source or contribute on GitHub.