Facile: The FastSim Architecture Simulation Language

Facile is a special purpose language for writing instruction level processor simulators in the FastSim v.2 simulation system. The design of Facile was motivated by the need for a simple ISA description and simulation language combined with features that allow FastSim's fast-forwarding optimization to be applied automatically.

Facile's ISA description is based on my previous work with SADL, which in turn was based on the New Jersey Machine-Code Toolkit, developed by Mary Fernández and Norman Ramsey. Descriptions in Facile can specify the binary encodings of instructions, instruction semantics, architectural and micro-architectural registers, and additional simulator behavior. These descriptions are very concise, and a basic SPARC-V9 simulator can be written with 658 lines of Facile code.

To support fast-forwarding, FastSim first analyzes the simulation code to find the static, run-time static, and dynamic parts of the simulation. Facile specifies that all arguments to the main function and data in the init variable is run-time static. Starting with this initial state, FastSim performs binding-time analysis (a form of data flow analysis) to label every operation in the main function as static, run-time static, or dynamic. See here for an example of FastSim's binding time analysis results.

Note that simulators written in Facile assume there is an implicit outer loop, which calls the main function repeatedly whenever it returns. main is called each time, with the values in init passed in as arguments. See the page on FastSim v.2 for more information on automated fast-forwarding.

More information about Facile:

Facile is derived from my earlier work on SADL. Click here for a look at SADL (the Spawn Architecture Description Language).

A snapshot of the FastSim v.2 source code (including the Facile compiler) is available for download here.

-- Return to FastSim home. --