An Out-Of-Order Processor Simulator

This simulator models a detailed out-of-order micro-architecture for the SPARC-V9 instruction set. In addition to an out-of-order pipeline, this simulator models non-blocking data caches, register renaming, branch prediction, speculative execution, and other detailed features.

Below are the Facile and C source files for this simulator:

• branch.c -- branch predictor.
• branch.fs -- branch predictor Facile interface.
• cache.c -- non-blocking cache simulator.
• cache.fs -- cache simulator Facile interface.
• dynamic.fs -- simulator main function.
• execute.fs -- execute instruction semantics.
• flags.fs -- misc. global flags.
• funits.fs -- constrain number of functional units.
• funits.h -- function unit numbers.
• instq.fs -- instruction queue definition.
• internal.h -- misc. C global declarations.
• ops.h -- internal opcode numbers.
• param.h -- simulator model parameters.
• rename_alloc.fs -- allocate physical registers.
• rename_data.fs -- data structures for register renaming.
• rename_decode.fs -- rename registers.
• rename_exec.fs -- access renamed register data.
• rename_init.fs -- initialize register renaming.
• rename_regs.h -- categories of registers.
• rename_type.fs -- register renaming data type declarations.
• sparc_v9_decode.fs -- decode target instructions.
• sparc_v9_enc.fs -- instruction encodings.
• sparc_v9_regs.fs -- register files access functions.
• xexit.c -- code to run on exit.

Follow this link to see the results of analyzing the simulator. The Facile compiler performs binding time analysis to determine which parts of the simulator can be skipped over by fast-forwarding. Annotated source code is generated in HTML format by the compiler to help visualize the results of its analysis.