Yu-Chi Lai
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CS Course Project DescriptionCS367 Introduction to Data Structures
CS564 Database Management Systems: Design and Implementation
CS640 Introduction to Computer Networks
CS755 VLSI System DesignsFinal Project Abstract.
The target of this project is to
implement a 16-entry destination reorder buffer (DRB) that might be used in an
implementation of timestamp snooping. Conceptually each message is tagged with a
logical timestamp. Messages may arrive at the DRB in any order, but may only be
forwarded to the device in increasing timestamp order. The primary purpose of
this buffer is to reorder message that arrive out of order. It is similar to
implement a priority queue. We select the method of logic priority selection
from the 16-entry buffer. The entire circuit consists of the input buffer,
parity checker, the input writing control logic, the output reading control
logic, the token control logic, parity generator, and the output buffer. The
functionality, performance, and so on are discussed in the following section.
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Contact: E-mail yu-chil@cae.wisc.edu Address 422 N. Segoe Rd. Apt. 73B, Madison, WI 53705 Phone H: 608-236-9763 CS: 608-262-7500
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