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arch
alpha
isa_traits.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Gabe Black
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*/
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#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
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#define __ARCH_ALPHA_ISA_TRAITS_HH__
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namespace
LittleEndianGuest {}
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#include "
arch/alpha/ipr.hh
"
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#include "
arch/alpha/types.hh
"
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#include "
base/types.hh
"
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#include "
cpu/static_inst_fwd.hh
"
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namespace
AlphaISA {
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using namespace
LittleEndianGuest;
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StaticInstPtr
decodeInst
(
ExtMachInst
);
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// Alpha Does NOT have a delay slot
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#define ISA_HAS_DELAY_SLOT 0
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const
Addr
PageShift
= 13;
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const
Addr
PageBytes
=
ULL
(1) <<
PageShift
;
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const
Addr
PageMask
= ~(
PageBytes
- 1);
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const
Addr
PageOffset
=
PageBytes
- 1;
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//
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// Translation stuff
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//
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const
Addr
PteShift
= 3;
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const
Addr
NPtePageShift
=
PageShift
-
PteShift
;
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const
Addr
NPtePage
=
ULL
(1) <<
NPtePageShift
;
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const
Addr
PteMask
=
NPtePage
- 1;
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// User Virtual
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const
Addr
USegBase
=
ULL
(0x0);
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const
Addr
USegEnd
=
ULL
(0x000003ffffffffff);
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// Kernel Direct Mapped
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const
Addr
K0SegBase
=
ULL
(0xfffffc0000000000);
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const
Addr
K0SegEnd
=
ULL
(0xfffffdffffffffff);
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// Kernel Virtual
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const
Addr
K1SegBase
=
ULL
(0xfffffe0000000000);
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const
Addr
K1SegEnd
=
ULL
(0xffffffffffffffff);
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//
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// Interrupt levels
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//
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enum
InterruptLevels
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{
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INTLEVEL_SOFTWARE_MIN
= 4,
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INTLEVEL_SOFTWARE_MAX
= 19,
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INTLEVEL_EXTERNAL_MIN
= 20,
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INTLEVEL_EXTERNAL_MAX
= 34,
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INTLEVEL_IRQ0
= 20,
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INTLEVEL_IRQ1
= 21,
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INTINDEX_ETHERNET
= 0,
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INTINDEX_SCSI
= 1,
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INTLEVEL_IRQ2
= 22,
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INTLEVEL_IRQ3
= 23,
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INTLEVEL_SERIAL
= 33,
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NumInterruptLevels
=
INTLEVEL_EXTERNAL_MAX
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};
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// EV5 modes
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enum
mode_type
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{
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mode_kernel
= 0,
// kernel
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mode_executive
= 1,
// executive (unused by unix)
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mode_supervisor
= 2,
// supervisor (unused by unix)
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mode_user
= 3,
// user mode
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mode_number
// number of modes
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};
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const
int
MachineBytes
= 8;
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// return a no-op instruction... used for instruction fetch faults
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// Alpha UNOP (ldq_u r31,0(r0))
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const
ExtMachInst
NoopMachInst
= 0x2ffe0000;
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// Memory accesses cannot be unaligned
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const
bool
HasUnalignedMemAcc
=
false
;
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const
bool
CurThreadInfoImplemented
=
true
;
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const
int
CurThreadInfoReg
=
AlphaISA::IPR_PALtemp23
;
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}
// namespace AlphaISA
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
AlphaISA::INTLEVEL_IRQ1
Definition:
isa_traits.hh:91
AlphaISA::K1SegEnd
const Addr K1SegEnd
Definition:
isa_traits.hh:76
AlphaISA::USegBase
const Addr USegBase
Definition:
isa_traits.hh:67
AlphaISA::NPtePage
const Addr NPtePage
Definition:
isa_traits.hh:63
AlphaISA::INTLEVEL_EXTERNAL_MIN
Definition:
isa_traits.hh:87
AlphaISA::K1SegBase
const Addr K1SegBase
Definition:
isa_traits.hh:75
static_inst_fwd.hh
ipr.hh
AlphaISA::PageShift
const Addr PageShift
Definition:
isa_traits.hh:51
AlphaISA::USegEnd
const Addr USegEnd
Definition:
isa_traits.hh:68
AlphaISA::decodeInst
StaticInstPtr decodeInst(ExtMachInst)
AlphaISA::CurThreadInfoImplemented
const bool CurThreadInfoImplemented
Definition:
isa_traits.hh:121
AlphaISA::INTLEVEL_SOFTWARE_MIN
Definition:
isa_traits.hh:84
AlphaISA::HasUnalignedMemAcc
const bool HasUnalignedMemAcc
Definition:
isa_traits.hh:119
AlphaISA::PageOffset
const Addr PageOffset
Definition:
isa_traits.hh:54
AlphaISA::NumInterruptLevels
Definition:
isa_traits.hh:99
AlphaISA::mode_supervisor
Definition:
isa_traits.hh:107
AlphaISA::PteShift
const Addr PteShift
Definition:
isa_traits.hh:61
AlphaISA::mode_number
Definition:
isa_traits.hh:109
AlphaISA::InterruptLevels
InterruptLevels
Definition:
isa_traits.hh:82
RefCountingPtr< StaticInst >
types.hh
AlphaISA::K0SegEnd
const Addr K0SegEnd
Definition:
isa_traits.hh:72
AlphaISA::NPtePageShift
const Addr NPtePageShift
Definition:
isa_traits.hh:62
AlphaISA::PageMask
const Addr PageMask
Definition:
isa_traits.hh:53
AlphaISA::INTLEVEL_EXTERNAL_MAX
Definition:
isa_traits.hh:88
AlphaISA::NoopMachInst
const ExtMachInst NoopMachInst
Definition:
isa_traits.hh:116
AlphaISA::mode_user
Definition:
isa_traits.hh:108
AlphaISA::PteMask
const Addr PteMask
Definition:
isa_traits.hh:64
AlphaISA::INTLEVEL_SERIAL
Definition:
isa_traits.hh:97
AlphaISA::INTINDEX_SCSI
Definition:
isa_traits.hh:93
AlphaISA::INTINDEX_ETHERNET
Definition:
isa_traits.hh:92
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
AlphaISA::ExtMachInst
uint64_t ExtMachInst
Definition:
types.hh:41
ULL
#define ULL(N)
uint64_t constant
Definition:
types.hh:50
AlphaISA::mode_executive
Definition:
isa_traits.hh:106
AlphaISA::INTLEVEL_IRQ3
Definition:
isa_traits.hh:95
AlphaISA::PageBytes
const Addr PageBytes
Definition:
isa_traits.hh:52
AlphaISA::MachineBytes
const int MachineBytes
Definition:
isa_traits.hh:112
AlphaISA::INTLEVEL_SOFTWARE_MAX
Definition:
isa_traits.hh:85
AlphaISA::CurThreadInfoReg
const int CurThreadInfoReg
Definition:
isa_traits.hh:122
AlphaISA::mode_kernel
Definition:
isa_traits.hh:105
AlphaISA::INTLEVEL_IRQ2
Definition:
isa_traits.hh:94
AlphaISA::IPR_PALtemp23
Definition:
ipr.hh:195
AlphaISA::INTLEVEL_IRQ0
Definition:
isa_traits.hh:90
AlphaISA::mode_type
mode_type
Definition:
isa_traits.hh:103
AlphaISA::K0SegBase
const Addr K0SegBase
Definition:
isa_traits.hh:71
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