Bradford M. Beckmann

Graduate Student
Computer Sciences Department
University of Wisconsin-Madison
1210 West Dayton Street
Madison, WI 53706-1685
USA

Email: beckmann@cs.wisc.edu
Office: CompSci and Stats 6366
Office Phone: (608) 265-2702

BS, 2000, University of Cincinnati, Electrical Engineering
MS, 2002, University of Wisconsin-Madison, Computer Science
PhD, 2006, University of Wisconsin-Madison, Computer Science
Advisor: David Wood
Thesis: pdf

Resume/CV: pdf  ps

 Picture of Brad Beckmann

Research Interests

As a member of the Wisconsin Multifacet Project, I'm researching interconnection networks and cache coherence protocols for chip multiprocessors under the constraints and opportunities of future IC technology.

Publications

  • ASR: Adaptive Selective Replication for CMP Caches,
    Bradford M. Beckmann, Michael R. Marty, and David A. Wood,
    39th International Symposium on Microarchitecture (MICRO), December 2006.
    Local copy: pdf
    Talk: ppt


  • Managing Wire Delay in Large Chip-Multiprocessor Caches,
    Bradford M. Beckmann and David A. Wood,
    37th International Symposium on Microarchitecture (MICRO), December 2004.
    Local copy: pdf
    Talk: htm and ppt

  • TLC: Transmission Line Caches,
    Bradford M. Beckmann and David A. Wood,
    36th International Symposium on Microarchitecture (MICRO), December 2003.
    Local copy: pdf
    Talk: htm and ppt

    • Tutorials

  • GEMS: Multifacet's General Execution-driven Multiprocessor Simulator,
    Michael R. Marty, Bradford Beckmann, Luke Yen, Alaa R. Alameldeen, Min Xu, and Kevin Moore
    Tutorial at the International Symposium on Computer Architecture (ISCA), June 2005.
    Talk: ppt

    • Links