CS 838-1 Fall 2003 Readings

(Preliminary -- Expect Changes!)

Last Updated: 8/27/2003

Introduction to CMPs: The Hydra project

• The Case for a Single-Chip Multiprocessor
  Kunle Olukotun, Basem A. Nayfeh , Lance Hammond, Ken Wilson and Kun-Yung Chang
  Proceedings of the Seventh International Symposium on Architectural Support for Parallel Languages and Operating Systems, October 1996.
  Available as: PDF Compressed PDF Postscript Compressed Postscript
   
• A Single-Chip Multiprocessor
  Lance Hammond, Basem A. Nayfeh and Kunle Olukotun
  IEEE Computer Special Issue on "Billion-Transistor Processors", September 1997.
  Available as: PDF Compressed PDF Postscript Compressed Postscript
   
• Evaluation of Design Alternatives for a Multiprocessor Microprocessor
  Basem A. Nayfeh , Lance Hammond and Kunle Olukotun
  Proceedings of the 23rd International Symposium on Computer Architecture, May 1996.
  Available as: PDF Compressed PDF Postscript Compressed Postscript
   
• Additional Hydra papers: http://www-hydra.stanford.edu/publications.shtml

Technology Drivers

• ITRS Roadmap -- Executive Summary. (other). Read the introduction and "Overall Roadmap Technology Characteristics", you may skim the rest quickly.
• Wire papers?

Application Drivers

• Impact of Chip-Level Integration on Performance of OLTP Workloads
  Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese
  In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture (HPCA-6), January 2000, Toulouse, France

• Using Cohort Scheduling to Enhance Server Performance,
  James Larus and Michael Parkes.
  Usenix Annual Technical Conference, June 2002
   
• Memory System Behavior of Java-Based Middleware,
  Martin Karlsson, Kevin E. Moore, Erik Hagersten and David A. Wood,
  9th International Symposium on High Performance Computer Architecture (HPCA), February 2003.
   
• A single-chip multiprocessor for multimedia: the MVP
  Guttag, K.   Gove, R.J.   Van Aken, J.R.  
  Computer Graphics and Applications, IEEE, Volume: 12,   Issue: 6, Nov 1992, pages: 53-64
   

Relevant Microarchitectures

• The Tera Computer System
  Robert Alverson, David Callahan, Daniel Cummings, Brian Koblenz, Allan Porterfield, Burton Smith   
  Proceedings of the1990 International Conference on Supercomputing
   
• Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks,
  C. Kozyrakis, D. Patterson.
  35th International Symposium on Microarchitecture, Instabul, Turkey, November 2002.
   
• Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading
  Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm, and Dean Tullsen
  ACM Transactions on Computer Systems, August 1997, pages 322-354.
   
• The MAJC Architecture: A Synthesis of Parallelism and Scalability.
  Marc Tremblay, Jeffrey Chan, Shailender Chaudhry, Andrew W. Conigliaro, Shing Sheung Tse:
  IEEE Micro 20(6): 12-25 (2000)

Other CMP systems

• Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing (html).
  Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese.
  In Proceedings of the 27th ACM International Symposium on Computer Architecture. June 2000, Vancouver, CA.
   
• More Piranha related papers: http://research.compaq.com/projects/Database/
   
• POWER4 system microarchitecture
  J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy,
  IBM J. of Research and Development, vol. 46, no., pp 5.
   
• The circuit and physical design of the POWER4 microprocessor
  J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson,
  IBM J. of Research and Development, vol. 46, no., pp 27.
   

Speculative Threading

·          Multiscalar Processors
G. S. Sohi, S. Breach, and T. N. Vijaykumar
22th International Symposium on Computer Architecture (ISCA-22), 1995.
 

·         Data Speculation Support for a Chip Multiprocessor
by Lance Hammond, Mark Willey, and Kunle Olukotun
Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, October 1998.

• The Jrpm System for Dynamically Parallelizing Java Programs,
  Mike Chen and Kunle Olukotun
  in Proceedings of the 30th International Symposium on Computer Architecture, San Diego, CA, June 2003.
  
  

Caching

• An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches,
  C.K. Kim, D.C. Burger, and S.W. Keckler.
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October, 2002.
  
  
• TLC: Transmission Line Caches,
  Bradford M. Beckmann and David A. Wood,
  36th International Symposium on Microarchitecture (MICRO), December 2003.
  
  
• MoSys Explains 1T-SRAM Technology,
  Microprocessor Report, Volume 13 No. 12
   

·     1T-SRAM-Q™: Quad-Density Technology Reins in Spiraling Memory Requirements
Mark-Eric Jones,
MoSys White Paper.

Reliability

• Detailed Design and Evaluation of Redundant Multithreading Alternatives.
  S. S. Mukherjee, M. Kontz, and S. K. Reinhardt.
  Proc. 29th Annual Int'l Symp. on Computer Architecture (ISCA), pp. 99-110, May 2002.
   
• Transient Fault Detection via Simultaneous Multithreading.
  S. K. Reinhardt and S. S. Mukherjee.
  Proc. 27th Annual Int'l Symp. on Computer Architecture (ISCA), June 2000.
   
• SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery,
  Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
  International Symposium on Computer Architecture (ISCA), May 2002.
   

Synchronization

• Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor,
  Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy,
  In 5th International Symposium on High Performance Computer Architecture, January, 1999

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Design Trade-offs

• Exploring the Design Space of Future CMPs,
  J. Huh, D.C. Burger, and S.W. Keckler.
  International Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2001.