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David A. Wood
Professor
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David A. Wood's On-line Publications
Year:
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2009,
2008,
2007,
2006,
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2005,
2004,
2003,
2002,
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2000,
1999,
1998,
1997,
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1996,
1995,
1994,
1993.
For other paper's from Prof. Wood's research groups, please see:
- TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory,
Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood
International Symposium on Computer Architecture (ISCA), June 2008.
Paper: pdf
Talk: ppt
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Computer system implementing synchronized broadcast using timestamps
Robert E. Cypher, David A. Wood, Mark D. Hill, Thomas M. Wicki,
U.S. Patent No 7,366,843 issued April 29, 2008.
- OS Support for Virtualizing Transactional Memory,
Michael M. Swift, Haris Volos, Neelam Goyal, Luke Yen, Mark D. Hill and David A Wood
Third ACM SIGPLAN Workshop on Transactional Memory (TRANSACT), February 2008.
Also appears as Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2008-1630,
February 2008.
Paper: pdf
Talk: ppt
- Performance Pathologies in Hardware Transactional Memory,
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood
IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, January-February 2008.
(Shorter, award version of ISCA2007 Paper)
Paper: pdf
- Performance Pathologies in Hardware Transactional Memory,
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood
International Symposium on Computer Architecture (ISCA), June 2007.
(Shorter, award version appears in Micro Top Picks Jan/Feb 2008)
Paper: pdf
Reference: ACM
Talk: ppt
Extended Talk: ppt
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System and method for enhancing communication between devices in a computer system
David A. Wood, RObert C. Zak, Jr., Monica Wong-Chan, Chistopher J. Jackson, Thomas P. Webber, Mark D. Hill
U.S. Patent No 7,225,383 issued May 29, 2007.
- LogTM-SE: Decoupling Hardware Transactional Memory from Caches,
Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood
International Symposium on High Performance Computer Architecture (HPCA), February 2007.
Paper: pdf
Reference: IEEE Xplore
Talk: ppt,
pdf
- Interactions
Between Compression and Prefetching in Chip Multiprocessors,
Alaa R. Alameldeen and David A. Wood
International Symposium on High Performance Computer Architecture (HPCA), February 2007.
Paper: pdf
Talk: ppt,
pdf
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Computer system implementing synchronized broadcast using skew control and queuing
Robert E. Cypher, Mark D. Hill, David A. Wood,
U.S. Patent No 7,136,980 issued November 14, 2006.
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ASR: Adaptive Selective Replication for CMP Caches,
Bradford M. Beckmann, Michael R. Marty, and David A. Wood,
39th International Symposium on Microarchitecture (MICRO),
December 2006.
Paper: pdf
Talk: ppt
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Supporting Nested Transactional Memory in LogTM,
Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift and David A. Wood
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
Paper: pdf
Reference:
ACM
Talk:
pdf,
ppt
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IPC Considered Harmful for Multiprocessor Workloads,
Alaa R. Alameldeen and David A. Wood,
IEEE Micro,
Jul-Aug 2006.
Paper: pdf
- LogTM: Log-based Transactional Memory,
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill and David A. Wood
International Symposium on High Performance Computer Architecture (HPCA), February 2006.
Paper: pdf
Reference: IEEE Xplore
Talk: ppt,
pdf
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Token based cache-coherence protocol
Martin, Milo M. K., Mark D. Hill, David A. Wood,
U.S. Patent No 6,981,097 issued December 27, 2005.
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Exploring Processor Design Options for Java Based Middleware,
Martin Karlsson, Kevin E. Moore, Erik Hagersten and David A. Wood,
34th International Conference on Parallel Processing (ICPP),
June 2005.
Paper: pdf
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Bandwidth-adaptive, hybrid, cache-coherence protocol,
Martin, Milo M. K., Daniel J. Sorin, Mark D. Hill, David A. Wood,
U.S. Patent No 6,883,070 issued April 19, 2005.
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Thread-Level Transactional Memory,
Kevin E. Moore, Mark D. Hill, and David A. Wood,
Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2005-1524,
March 2005.
Technical Report: pdf
- Improving Multiple-CMP Systems Using Token Coherence,
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M.K. Martin and David A. Wood,
International Symposium on High Performance Computer Architecture (HPCA), February 2005.
Paper: pdf
Talk:
ppt
Extended Talk:
ppt
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Method and device for a context-based memory management system,
Boris Ostrovsky, Daniel R. Cassiday, John R. Feehrer, David A. Wood, Pazhani Pillai, Christopher J. Jackson, Mark Donald Hill,
U.S. Patent No 6,826,671 issued November 30, 2004.
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Managing Wire Delay in Large Chip-Multiprocessor Caches,
Bradford M. Beckmann and David A. Wood,
37th International Symposium on Microarchitecture (MICRO),
December 2004.
Paper: pdf
Talk:
htm and
ppt
- Adaptive Cache Compression for High-Performance Processors,
Alaa R. Alameldeen and David A. Wood,
International Symposium on Computer Architecture (ISCA), June 2004.
Paper: pdf
Talk:
ppt
Details of the compression algorithm are available in:
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Using Speculation to Simplify Multiprocessor Design,
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
International Parallel and Distributed Processing Symposium (IPDPS),
April 2004.
Paper: pdf
Talk:
ppt
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Token Coherence: A New Framework for Shared-Memory Multiprocessors,
Milo M.K. Martin, Mark D. Hill and David A. Wood,
IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences,
November-December 2003.
Paper: pdf
Original ISCA03 Paper: pdf
Token Coherence Bibliography: html
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Addressing Workload Variability in Architectural Simulations,
Alaa R. Alameldeen and David A. Wood,
IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences,
November-December 2003.
Paper: pdf
Original HPCA03 Paper: pdf
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TLC: Transmission Line Caches,
Bradford M. Beckmann and David A. Wood,
36th International Symposium on Microarchitecture (MICRO),
December 2003.
Paper: pdf
Talk:
htm and
ppt
- Token Coherence: Decoupling Performance and Correctness,
Milo M. K. Martin, Mark D. Hill, and David A. Wood,
International Symposium on Computer Architecture (ISCA), June 2003.
Paper: pdf
Reference:
ACM
Talk:
pdf,
ppt
Shorter IEEE Micro Top Picks Paper: pdf
Token Coherence Bibliography: html
- Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multiprocessors,
Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood,
International Symposium on Computer Architecture (ISCA), June 2003.
Paper: pdf
Reference:
ACM
Talk:
pdf,
ppt
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Simulating a $2M Commercial Server on a $2K PC,
Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood,
IEEE Computer, February 2003.
Paper: pdf
Talk:
ppt
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Variability in Architectural Simulations of Multi-threaded Workloads,
Alaa R. Alameldeen and David A. Wood,
9th International Symposium on High Performance Computer Architecture (HPCA),
February 2003.
Paper: pdf
Talk:
ppt, pdf
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Memory System Behavior of Java-Based Middleware,
Martin Karlsson, Kevin E. Moore, Erik Hagersten and David A. Wood,
9th International Symposium on High Performance Computer Architecture (HPCA),
February 2003.
Paper: pdf
Talk: pdf, ppt
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Dynamic Verification of End-to-End Multiprocessor Invariants,
Daniel J. Sorin, Mark D. Hill, and David A. Wood,
International Conference on Dependable Systems and Networks (DSN, formerly FTCC), June 2003.
Paper: pdf
Talk:
ppt
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Cache with dynamic control of sub-block fetching,
Douglas C. Burger and David A. Wood,
U.S. Patent No 6,557,080 issued April 29, 2003.
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Full-System Timing-First Simulation,
Carl J. Mauer, Mark D. Hill, and David A. Wood,
ACM SIGMETRICS, June 2002.
Paper: pdf
Reference:
ACM
Talk:
pdf and
ppt
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Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol,
Daniel J. Sorin, Manoj Plakal, Anne E. Condon, Mark D. Hill, Milo M. K. Martin and David A. Wood,
IEEE Transactions on Parallel and Distributed Systems, June 2002 (vol 13, number 6).
(Previously available as Dept. of Computer Sciences Technical Report
CS-TR-2000-1412, March 2000.)
Paper: pdf
Online protocol examples in html
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SafetyNet: Improving the Availability of
Shared Memory Multiprocessors with Global Checkpoint/Recovery,
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
International Symposium on Computer Architecture (ISCA), May 2002.
Paper: pdf
Reference:
IEEE
Talk:
ppt
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Memory Characterization of the ECperf Benchmark,
Martin Karlsson, Kevin E. Moore, Erik Hagersten, and David A. Wood,
Workload on Memory Performance Issues (WMPI), 2002.
Paper: pdf.
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Evaluating Non-deterministic Multi-threaded Commercial Workloads,
Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood,
Workshop On Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2002.
Paper: pdf
Talk:
pdf and
ppt
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Bandwidth Adaptive Snooping,
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood,
8th International Symposium on High Performance Computer Architecture (HPCA),
February 2002.
Paper: pdf
Talk:
pdf and
ppt
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Timestamp Snooping: An Approach for Extending SMPs,
Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen,
Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill,
and David A. Wood,
Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.
Paper: pdf
and ps
Reference:
ACM
Talk: pdf
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Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance,
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
Dept. of Computer Sciences Technical Report CS-TR-2000-1420, October 2000.
Technical Report: pdf
and ps
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Fast and Portable Parallel Architecture Simulators: Wisconsin Wind Tunnel II,
Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike
Litzkow, Steven Huss-Lederman, Mark D. Hill, James R. Larus, and David
A. Wood,
IEEE Concurrency, October-December 2000.
Paper: pdf.
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Cachable interface control registers for high speed data transfer,
David A. Wood, Steven K. Reinhardt, Shubhendu S. Mukherjee,
Babak Falsafi, Mark D. Hill, and Robert W. Pfile,
United States Patent 5,951,657 issued September 14, 1999.
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Methods and apparatus for substantially memory-less coherence transformer
for connecting computer node coherence domains,
Erik E. Hagersten, Mark D. Hill, and David A. Wood,
U.S. Patent No. 5,940,860 issued August 17, 1999.
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DBMSs on a modern processor: Where does time go?,
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and David A. Wood,
International Conference on Very Large Databases (VLDB), September 1999.
Paper: pdf
and ps
Talk: ppt
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Multicast Snooping: A New Coherence Method Using a Multicast Address Network,
E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David A. Wood.
International Symposium on Computer Architecture (ISCA), May 1999.
Paper:
pdf and
ps
Reference:
ACM
Talk:
pdf and
ps
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Hybrid NUMA COMA caching system and methods for selecting between caching modes,
David A. Wood and Erik E. Hagersten,
U.S. Patent No. 5,893,144, April 6, 1999.
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Parallel Dispatch Queue: A Queue-Based Programming Abstraction To
Parallelize Fine-Grain Communication Protocols
Babak Falsafi and David A. Wood
(Proceedings of the 5th International Symposium on
High-Performance Computer Architecture (HPCA-5), 1999).
Method and apparatus for a coherence transformer for connecting computer system coherence domains,
Erik E. Hagersten, Mark D. Hill, and David A. Wood,
U.S. Patent No. 5,860,109, Jan 12, 1999.
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Hardware Support for Flexible Distributed Shared Memory,
Steven K. Reinhardt, Robert Pfile, and David A. Wood,
(IEEE Transactions on Computers, Vol. 47, No. 10, October 1998,
pp. 1056-1072).
Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains,
Erik E. Hagersten, Mark D. Hill, and David A. Wood,
U.S. Patent No. 5,829,034, October 27, 1998.
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Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory,
Ioannis Schoinas, Babak Falsafi,
Mark D. Hill, James R. Larus, David A. Wood
(International Conference on Parallel Architectures and Compilation
Techniques (PACT), Oct 1998).
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Analytical Evaluation of Shared-Memory Parallel Systems
with ILP Processors,
Daniel Sorin, Sarita Adve, Vijay Pai, Mary Vernon, David Wood.
Proceedings of the 25th International Symposium
on Computer Architecture (ISCA), June 1998.
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Reflections on "Tempest and Typhoon: User-level Shared Memory",
Steven K. Reinhardt, James R. Larus, and David A. Wood,
In 25 years of the International Symposia of Computer Architecture:
Selected Papers, ed. Gurindar Sohi, pp. 98-101, 1998.
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Reactive NUMA: A Design for Unifying S-COMA with CC-NUMA,
Babak Falsafi and David A. Wood,
ACM/IEEE International Symposium on Computer Architecture (ISCA),
June 1997.
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Relaxed Consistency and Coherence Granularity in DSM Systems:
A Performance Evaluation,
Yuanyuan Zhou, Liviu Iftode, Jaswinder Pal Singh, Kai Li, Brian R. Toonen,
Ioannis Schoinas, Mark D. Hill, David A. Wood,
ACM Symposium on Principles and Practices of Parallel Programming,
June 1997.
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Wisconsin Wind Tunnel II: A Fast and Portable Parallel Architecture
Simulator
Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow,
Steve Huss-Lederman, Mark D. Hill, James R. Larus, and David A. Wood,
1997 Workshop on Performance Analysis and its Impact on Design (PAID-97),
June 1997.
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Modeling Cost/Performance of a Parallel Computer Simulator,
Babak Falsafi and David A. Wood,
ACM Transactions on Modeling
and Computer Simulation, January 1997.
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Active Memory: A New Abstraction For Memory System Simulation
Alvin R. Lebeck and David A. Wood,
ACM Transactions on Modeling and Computer Simulation, January 1997.
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Scheduling Communication on an SMP Node Parallel Machine,
Babak Falsafi and David A. Wood,
IEEE International Symposium on High Performance Computer
Architecture (HPCA), February 1997.
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Decoupled Hardware Support for Distributed Shared Memory
Steven K. Reinhardt, Robert W. Pfile, and
David A. Wood,
ACM/IEEE International Symposium on Computer Architecture (ISCA),
May 1996
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Coherent Network Interfaces for Fine-Grain Communication
Shubhendu S. Mukherjee and Babak Falsafi and Mark D. Hill and
David A. Wood,
ACM/IEEE International Symposium on Computer Architecture (ISCA),
May 1996
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Synchronization Hardware for Networks of Workstations: Performance vs. Cost
Rahmat S. Hyder and David A. Wood,
ACM/IEEE International Conference on Supercomputing (ICS),
May 1996
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Paging Tradeoffs in Distributed Shared-Memory Multiprocessors,
Douglas Burger, Rahmat Hyder, Barton Miller, and David A. Wood,
Journal of SuperComputing, vol. 10, pp. 87-104, 1996.
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Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
Alvin R. Lebeck and David A. Wood,
ACM/IEEE International Symposium on Computer Architecture (ISCA),
June 1995
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Active Memory: A New Abstraction For Memory System Simulation
Alvin R. Lebeck and David A. Wood,
Proceedings of the 1995 ACM Sigmetrics Conference
on Measurement and Modeling of Data, May 1995.
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Accuracy vs. Performance in Parallel Simulation of Interconnection Networks,
Douglas C. Burger and David A. Wood.
In the proceedings of the 9th International Parallel Processing Symposium, April, 1995.
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Cost-Effective Parallel Computing,
David A. Wood and Mark D. Hill,
IEEE Computer, Vol 28. No. 2, February 1995, pp. 69-72.
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Application-Specific Protocols for User-Level Shared Memory,
Babak Falsafi, Alvin Lebeck, Steven Reinhardt, Ioannis Schoinas,
Mark Hill, James Larus, Anne Rogers, and David Wood,
In Proceedings of Supercomputing '94.
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Fine-grain Access Control for Distributed Shared Memory,
Ioannis Schoinas, Babak Falsafi, Alvin Lebeck, Steven Reinhardt,
James Larus, and David Wood,
Proceedings of ASPLOS VI.
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Tempest and Typhoon: User-Level Shared Memory,
Steven Reinhardt, James Larus, and David Wood,
Proceedings of Int'l Symposium on Computer Architecture, 1994.
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Cache Profiling and the SPEC Benchmarks: A Case Study,
Alvin R. Lebeck and David A. Wood,
pages 15-26,
IEEE COMPUTER,
October 1994
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The Wisconsin Wind Tunnel Project: An Annotated Bibliography,
Mark D. Hill, James R. Larus, David A. Wood,
Computer Architecture News, v. 22, n. 5, December 1994.
On-line version revised frequently.
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Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors,
Mark D. Hill, James R. Larus, Steven K. Reinhardt, David A. Wood,
ACM Transactions on Computer Systems (TOCS), November 1993.
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Mechanisms for Cooperative Shared Memory,
David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus,
Alvin R. Lebeck, James Lewis,
Shubhendu Mukherjee, Sabbarao Palacharla, Steven K. Reinhardt,
20th International Symposium on Computer Architecture,
pp. 156-168, May 1993.
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The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers,
Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck,
James Lewis, David A. Wood,
Proceedings of the 1993 ACM Sigmetrics Conference
on Measurement and Modeling of Data, pp. 48-60, May 1993.
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Kernel Support for the Wisconsin Wind Tunnel,
Steven K. Reinhardt, Babak Falsafi, and David A. Wood,
Proceedings of the Second Usenix Symposium on Microkernels and Other Kernel Architectures,
pp. 73-89, September 1993,
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Wisconsin Architectural Research Tool Set (WARTS),
Mark D. Hill, James R. Larus, Alvin R. Lebeck, Madhusudhan Talluri,
David A. Wood,
Computer Architecture News (CAN), August 1993.
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