Suchita Pati

PhD Student
HAL Research Lab
Department of Computer Sciences
University of Wisconsin-Madison

Contact

Email: spati [AT] cs [DOT] wisc [DOT] edu
Room 6372
Computer Sciences
1210 W. Dayton St.
Madison, WI 53706

About Me

I am a Member of Technical Staff at AMD Research & Advanced Development. I received my PhD and MS from the Department of Computer Sciences at University of Wisconsin-Madison where I was advised by Prof. Matt Sinclair. My research interests are in Systems for ML, with specific focus on Transformers/LLMs.

Before grad school, I was a Design Engineer at AMD India in the Server Performance Group. I received my bachelor's degree in Electrical and Electronics Engineering from BITS-Pilani, Hyderabad, India in 2015.

Recent News

Jul 2026: Paper on expanding DMA offloads to latency-bound ML communication DMA-Latte accepted at MICRO 2026.

Dec 2025: Paper on Fine-grained DMA-based Communication available on ArXiv.

Mar 2025: Paper on improving concurrent GEMM executions on GPUs using GOLDYLOC accepted at ACM TACO.

Mar 2025: Paper on improving concurrent compute and communication using DMA engines using ConCCL accepted at ISPASS 2025.

Apr 2024: Presented the paper, T3, on hiding communication in distributed LLMs at ASPLOS 2024.

Feb 2024: Defended my PhD thesis!

Feb 2024: Paper on Just-In-Time quantization for ML using PIM accepted at MLSys 2024.

Dec 2023: Paper on hiding communication in distributed LLMs accepted at ASPLOS 2024.

Oct 2023: Presented work on communication in distributed LLM (Tale of 2C's) at IISWC 2023.

Aug 2023: Paper on modeling and analysis of communication in distributed LLMs accepted at IISWC 2023.

Jun 2023: Joined AMD Research.

Publications

DMA-Latte: Expanding the Reach of DMA Offloads to Latency-bound ML Communication [PDF]
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Ryan Quach, Saleel Kudchadker, Mohamed Assem Ibrahim
To Appear at IEEE/ACM International Symposium on Microarchitecture (MICRO) 2026

Design Space Exploration of DMA based Finer-Grain Compute Communication Overlap [PDF]
Shagnik Pal, Shaizeen Aga, Suchita Pati, Mahzabeen Islam, Lizy K. John
ArXiv 2025

GOLDYLOC: Global Optimizations & Lightweight Dynamic Logic for Concurrency [PDF]
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matt Sinclair
ACM Transactions on Architecture and Code Optimization (TACO) 2025

ConCCL: Optimizing ML Concurrent Computation and Communication with GPU DMA Engines [PDF]
Anirudha Agrawal, Shaizeen Aga, Suchita Pati, Mahzabeen Islam
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2025

JIT-Q: Just-in-time Quantization with Processing-In-Memory for Efficient ML Training [PDF]
Mohamed Assem Ibrahim, Shaizeen Aga, Ada Li, Suchita Pati, Mahzabeen Islam
Proceedings of Machine Learning and Systems (MLSys) 2024

T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives [PDF]
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matt Sinclair
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2024

Tale of Two Cs: Computation vs. Communication Scaling for Future Transformers on Future Hardware [PDF]
Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matt Sinclair
ArXiv preprint arXiv 2302.02825, January 2023
IEEE International Symposium on Workload Characterization (IISWC) 2023

Demystifying BERT: System Design Implications [PDF], preprint>
Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matt Sinclair
ArXiv preprint arXiv 2104.08335, April 2021
IEEE International Symposium on Workload Characterization (IISWC) 2022

SeqPoint: Identifying Representative Iterations of Sequence-based Neural Networks [PDF], preprint on ArXiv .
Suchita Pati, Shaizeen Aga, Matt Sinclair, Nuwan Jayasena
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2020

Analyzing Machine Learning Workloads Using a Detailed GPU Simulator [PDF]
Jonathan Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor Aamodt
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2019

Analyzing Machine Learning Workloads Using a Detailed GPU Simulator [PDF]
Jonathan Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor Aamodt
ArXiv preprint arXiv:1811.08933, November 2018

DARTS: Performance-counter driven sampling using binary translators [PDF]
Rajesh Kumar, Suchita Pati, Kanishka Lahiri
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2017

Workshops and Misc

Improving GPU Utilization in ML Workloads Through Finer-Grain Synchronization [PDF]
Reese Kuper, Suchita Pati, Matthew D. Sinclair
The 3rd Young Architect Workshop co-located w/ ASPLOS (YArch-2021)

Exploring GPU Architectural Optimizations for RNNs [PDF]
Suchita Pati, Matthew D. Sinclair
The 1st Young Architect Workshop co-located w/ HPCA (YArch-2019)

Simulating Deep Learning Workloads in GPGPU-Sim [PDF]
Suchita Pati and Matthew D. Sinclair
UW Computer Architecture Affiliates 2018

Other Projects

Tail Latency and Predictable Local Storage Systems [PDF]
Distributed Systems (CS739)
Transparent Compression for Flash SSDs [PDF]
Advanced Operating Systems (CS736)
Effective Prefetching for Multicore/Multiprocessor Systems [PDF]
Advanced Computer Architecture II (CS757)
HOT Predictions Effects of Context Switching [PDF]
Advanced Computer Architecture I (CS752)

CV

Here is my CV