Current Interests:

Technical Areas: Computer Architecture, Operating Systems, Computer Networks, etc.

Other Technical Fascinations:

Quantum Computing, Nanotech Architectures;  
Digital Divide, Revolutionary User Interfaces

Current Activity:

Research Staff Member, IBM India Research Lab., Bangalore.
Researching Multi-Core and 3D Processor Architectures. Previously researched processor architecture for the Blue Gene-Q (BGQ) Supercomputer team.

Recent Activity:

Built Oracle's first formal, tiny applied-research team. Team conducted applied research in the Real-Time Collaboration space and prototyped ideas in the context of the product code. Team was based at Oracle, Bangalore, India. (Dec.2003 - Feb.2006)

Guest Editorials:

"Early 21st Century Processors", by Sriram Vajapeyam and Mateo Valero, Guest Editorial, IEEE Computer, April 2001.

"Computational Science ", by Sriram Vajapeyam and Rudra Pratap, Introduction to Special Section of  Current Science , Vol 78, No 7, 10th April 2000.

Panel Discussions:

ISCA'04 Panel: Panelist. Topic: Supporting ILP in tiled architectures: wasted effort, or a good idea? [Slides]

HiPC'99 Panel: Moderator. Topic: Whither Indian Computer Science R&D?

Tutorials Taught:

Conferences:

General Co-Chair: HiPC 2000 and HiPC 2001.

Visiting Positions Held:

Select Publications:

Multi-core (Tiled) Processors. CDE: A Compiler-Driven, Dependence-Centric, Eager-Executing Architecture for the Billion Transistor Era , published at the Workshop on Complexity-Effective Design held at ISCA'03. Evangelised at the ISCA 2004 panel discussion on ILP architectures. [Slides]

Trace Processors, a novel micro-architecture. Published under the title " Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences " in the 1997 IEEE/ACM International Symposium on Computer Architecture (ISCA-24).
Old webpage of Trace Processors project .

Dynamic Vectorization. A hardware method for transparently converting program loops to vector form during execution. Published under the title " Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs " in the 1999 IEEE/ACM International Symposium on Computer Architecture (ISCA-26).

Sub-tagged Caches. Motivational study published as ""Page-Level Behavior of Cache Contention ",  S. Tambat, S. Vajapeyam, in TCCA Computer Architecture Letters, July 2002. Details presented in the technical report " Subtagged Caches: Study of Variable Cache-Block Size Emulation ", S. Tambat, S. Vajapeyam,  July 2001.

"Multiprocessor Cache Coherence. Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications ", by S. Tambat and S. Vajapeyam, Int'l. Conf. on Parallel Processing (ICPP) August 2000.

Alma Maters:

       University of Wisconsin, Madison

       IIT (Indian Institute of Technology), Madras

        Govinda Dasa Pre-University College, Surathkal, India

        Vidyadayinee High School, Surathkal, India