Sriram Vajapeyam's Alumnus Webpage


Freelance Researcher



UW-Madison Alumnus (1991 Ph.D.)
IIT-Madras Alumnus (1985 B.Tech.)
Email: sriram at alumni dot cs dot wisc dot edu, sriram_vajapeyam at yahoo


Current Professional Activity:

Freelance Researcher
Freelancing since Feb.2010.      

Chief Interests:

R&D: Computer Systems, especially Computer Architecture and High-Performance Computing
Education: Computer-Aided Learning and Teaching

Technical Fascinations:

Many! ("Fascination" as in: "I find work fascinating; I can sit and watch it for hours!" -- Dennis The Menace!)
Quantum Computing, Nanotech Architectures; AI, especially Machine Learning; Information Theory, Privacy Preservation in Data Mining; etc, etc.

 

 

Some Recent Publications and Patents:

* Distributed Procedure Execution in Multi-Core Processors
US Patent No. 9,483,318, issued November 1st, 2016.
* A Probabilistic Framework for Locating Cached Data on 1000-core Processors
US Patent No. 9,405,691, issued August 2nd, 2016.
* Trace-Core Processors
Prior Art Disclosure IPCOM000199882D 20 Sept.2010. (Original IBM Invention Disclsoure: Nov.2008.)
* Aspect-Oriented Parallel Programming Language Extensions
US Patent No. 8,694,962, issued April 8, 2014, filed April 30, 2009. (Original IBM Invention Disclosure: Nov.2008.)

Misc. writings:

  • Understanding Shannon's Entropy metric for Information
  •  

     

    Past Professional Activity:

    * Research Staff Member, IBM India Research Lab., Bangalore. (July 2006 -- Jan. 2010)
    Researched Multi-Core Processor Architectures (2009). Previously researched processor architecture for the Blue Gene-Q (BGQ) Supercomputer team (mid-2006 - 2008).
    * Director, Oracle Real-Time Collaboration Research Group.
    Built Oracle's first formal, tiny applied-research team. Team conducted applied research in the Real-Time Collaboration space and prototyped ideas in the context of the product code. Team was based at Oracle, Bangalore, India. (Dec.2003 - Feb.2006)

     

     

    Guest Editorials:

    "Early 21st Century Processors", by Sriram Vajapeyam and Mateo Valero, Guest Editorial, IEEE Computer, April 2001.

     

    "Computational Science ", by Sriram Vajapeyam and Rudra Pratap, Introduction to Special Section of  Current Science , Vol 78, No 7, 10th April 2000.

     

     

    Panel Discussions:

    ISCA'04 Panel: Panelist. Topic: Supporting ILP in tiled architectures: wasted effort, or a good idea? [Slides]

     

    HiPC'99 Panel: Moderator. Topic: Whither Indian Computer Science R&D?

     

     

    Tutorials Taught:

    ISCA'98; ASPLOS'98; ISCA'99; ISCA'01; HiPC'02. [Details to be filled.]

     

     

    Conferences:

    General Co-Chair: HiPC 2000 and HiPC 2001.

     

     

    Visiting Positions Held:

    MIT (June-Aug.'97); UW-Madison (May '97);
    UPC Barcelona (summers '02, '03); USC-LA (summer 2000);
    Intel MRL (Feb-Mar '01, May '01); Cray Research (summer 1994);
    ADI, Bangalore (Aug.'00-Jan.'01); ACRI, France (summer 1993);

     

     

    Select Publications:

    Multi-core (Tiled) Processors. CDE: A Compiler-Driven, Dependence-Centric, Eager-Executing Architecture for the Billion Transistor Era , published at the Workshop on Complexity-Effective Design held at ISCA'03. Evangelised at the ISCA 2004 panel discussion on ILP architectures. [Slides]

     

    Trace Processors, a novel micro-architecture. Published under the title " Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences " in the 1997 IEEE/ACM International Symposium on Computer Architecture (ISCA-24).
    Old webpage of Trace Processors project .

     

    Dynamic Vectorization. A hardware method for transparently converting program loops to vector form during execution. Published under the title " Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs " in the 1999 IEEE/ACM International Symposium on Computer Architecture (ISCA-26).

     

    Sub-tagged Caches. Motivational study published as ""Page-Level Behavior of Cache Contention ",  S. Tambat, S. Vajapeyam, in TCCA Computer Architecture Letters, July 2002. Details presented in the technical report " Subtagged Caches: Study of Variable Cache-Block Size Emulation ", S. Tambat, S. Vajapeyam,  July 2001.

     

    "Multiprocessor Cache Coherence. Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications ", by S. Tambat and S. Vajapeyam, Int'l. Conf. on Parallel Processing (ICPP) August 2000.

     

     

    Alma Maters:

           University of Wisconsin, Madison

     

    IITM       IIT (Indian Institute of Technology), Madras

     

            Govinda Dasa Pre-University College, Surathkal, India

     

            Vidyadayinee High School, Surathkal, India

     

            KREC Higher Primary School, Surathkal, India




    <Updated August 2016>
    <Updated July 2011>

     

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