Processors: HAL Computers, a US-based Fujitsu subsidiary, attempted to build a commercial Trace Processor (ISCA'97) over multiple years in the late 1990s. This was described in an article by a leading industry publication, Microprocessor Report ,www.mdronline.com, although the article failed to credit this author for the original proposal of Trace Processors (ISCA'97), instead crediting follow-up papers by other researchers. (The error was subsequently acknowledged in personal communication).

Software Fault Tolerance: Sriram Vajapeyam's seed ideas on dynamic value-tracking and error handling in programs directly motivated Anant Agarwal of MIT into starting up InCert Corp., a Cambridge, Massachusetts based startup company in 1997, that provided transparent, on-the-fly support software for application fault-handling. The original idea was to provide an automatic assistant for addressing the Y2K problem but the company ended up addressing the mainframe reliability market instead. InCert Corp. was subsequently acquired by Geodesic Systems of Chicago, which in turn was acquired by Veritas that was then acquired by Symantec.

- Information Theory
- AI: Machine Learning, Deep Learning
- Privacy Preservation in Data Mining
- Quantum Computing,  ...   etc, etc.

Multi-core (Tiled) Processors. CDE: A Compiler-Driven, Dependence-Centric, Eager-Executing Architecture for the Billion Transistor Era , published at the Workshop on Complexity-Effective Design held at ISCA'03. Evangelised at the ISCA 2004 panel discussion on ILP architectures. [Slides]

Trace Processors, a novel micro-architecture. Published under the title " Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences " in the 1997 IEEE/ACM International Symposium on Computer Architecture (ISCA-24).
Old webpage of Trace Processors project .

Dynamic Vectorization. A hardware method for transparently converting program loops to vector form during execution. Published under the title " Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs " in the 1999 IEEE/ACM International Symposium on Computer Architecture (ISCA-26).

Sub-tagged Caches. Motivational study published as ""Page-Level Behavior of Cache Contention ",  S. Tambat, S. Vajapeyam, in TCCA Computer Architecture Letters, July 2002. Details presented in the technical report " Subtagged Caches: Study of Variable Cache-Block Size Emulation ", S. Tambat, S. Vajapeyam,  July 2001.

"Multiprocessor Cache Coherence. Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications ", by S. Tambat and S. Vajapeyam, Int'l. Conf. on Parallel Processing (ICPP) August 2000.

          US Patent Number            Title

  1     US Patent 9,940,170          Dynamically managing distribution of data and computation across cores for sequential programs  

  2     US Patent 9,916,086          Content-addressable memory device  

  3     US Patent 9,864,709          Data transfer in a multi-core processor  

  4     US Patent 9,811,469          Sequential access of cache data  

  5     US Patent 9,804,896          Thread migration across cores of a multi-core processor  

  6     US Patent 9,785,568          Cache lookup bypass in multi-level cache systems  

  7     US Patent 9,483,318          Distributed procedure execution in multi-core processors  

  8     US Patent 9,405,691          Locating cached data in a multi-core processor  

  9     US Patent 8,694,962          Aspect-oriented parallel programming language extensions (@IBM)

10     US Patent 7,363,467          Dependence-chain processing using trace descriptors having dependency descriptors (@Intel)

11     Prior Art Disclosure IPCOM000199882D Trace-Core Processors. 20 Sept.2010. (Original IBM Invention Disclsoure: Nov.2008.) (@IBM)

- ISCA'98
- ASPLOS'98
- ISCA'99
- ISCA'01
- HiPC'02.

"Early 21st Century Processors", by Sriram Vajapeyam and Mateo Valero, Guest Editorial, IEEE Computer, April 2001.

"Computational Science ", by Sriram Vajapeyam and Rudra Pratap, Introduction to Special Section of  Current Science , Vol 78, No 7, 10th April 2000.

ISCA'04 Panel: Panelist. Topic: Supporting ILP in tiled architectures: wasted effort, or a good idea? [Slides]

HiPC'99 Panel: Organizer. Topic: Whither Indian Computer Science R&D?

- MIT (June-Aug.'97);

- UW-Madison (May '97);

- Intel MRL (Feb-Mar '01, May '01);

- Cray Research (summer 1994);

- ADI, Bangalore (Aug.'00-Jan.'01);

- UPC Barcelona (summers '02, '03);

- USC-LA (summer 2000);

- ACRI, France (summer 1993);

- Research Staff Member, IBM India Research Lab., Bangalore. (July 2006 -- Jan. 2010)
Researched Multi-Core Processor Architectures (2009).
Previously researched processor architecture for the Blue Gene-Q (BGQ) Supercomputer team (mid-2006 - 2008).

- Director, Oracle Real-Time Collaboration Research Group. (Dec.2003 - Feb.2006)
Built Oracle's first formal, tiny applied-research team. Team conducted applied research in the Real-Time Collaboration space and prototyped ideas in the context of the product code. Team was based at Oracle, Bangalore, India.

- Indian Academia (Nov.1992 - July 2001)

- Cray Research (Aug.1991 - Oct.1992)

       University of Wisconsin, Madison

       IIT (Indian Institute of Technology), Madras

        Govinda Dasa Pre-University College, Surathkal, India

        Vidyadayinee High School, Surathkal, India

        KREC Higher Primary School, Surathkal, India