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BankedArray.hh
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1 /*
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28  * Author: Brad Beckmann
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31 
32 #ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
33 #define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
34 
35 #include <vector>
36 
39 #include "sim/core.hh"
40 
42 {
43  private:
44  unsigned int banks;
46  unsigned int bankBits;
47  unsigned int startIndexBit;
49 
51  {
52  public:
54  int64_t idx;
57  };
58 
59  // If the tick event is scheduled then the bank is busy
60  // otherwise, schedule the event and wait for it to complete
62 
63  unsigned int mapIndexToBank(int64_t idx);
64 
65  public:
66  BankedArray(unsigned int banks, Cycles accessLatency,
67  unsigned int startIndexBit, RubySystem *rs);
68 
69  // Note: We try the access based on the cache index, not the address
70  // This is so we don't get aliasing on blocks being replaced
71  bool tryAccess(int64_t idx);
72 
73  void reserve(int64_t idx);
74 
75  Cycles getLatency() const { return accessLatency; }
76 };
77 
78 #endif
unsigned int mapIndexToBank(int64_t idx)
Definition: BankedArray.cc:95
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
bool tryAccess(int64_t idx)
Definition: BankedArray.cc:53
Cycles accessLatency
Definition: BankedArray.hh:45
std::vector< AccessRecord > busyBanks
Definition: BankedArray.hh:61
unsigned int startIndexBit
Definition: BankedArray.hh:47
STL vector class.
Definition: stl.hh:40
unsigned int banks
Definition: BankedArray.hh:44
unsigned int bankBits
Definition: BankedArray.hh:46
uint64_t Tick
Tick count type.
Definition: types.hh:63
BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit, RubySystem *rs)
Definition: BankedArray.cc:37
void reserve(int64_t idx)
Definition: BankedArray.cc:69
Cycles getLatency() const
Definition: BankedArray.hh:75
RubySystem * m_ruby_system
Definition: BankedArray.hh:48
Bitfield< 9, 8 > rs
Definition: miscregs.hh:1560

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