#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"

Enumerations
enum	AlphaISA::InterruptLevels { AlphaISA::INTLEVEL_SOFTWARE_MIN = 4, AlphaISA::INTLEVEL_SOFTWARE_MAX = 19, AlphaISA::INTLEVEL_EXTERNAL_MIN = 20, AlphaISA::INTLEVEL_EXTERNAL_MAX = 34, AlphaISA::INTLEVEL_IRQ0 = 20, AlphaISA::INTLEVEL_IRQ1 = 21, AlphaISA::INTINDEX_ETHERNET = 0, AlphaISA::INTINDEX_SCSI = 1, AlphaISA::INTLEVEL_IRQ2 = 22, AlphaISA::INTLEVEL_IRQ3 = 23, AlphaISA::INTLEVEL_SERIAL = 33, AlphaISA::NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }

enum	AlphaISA::mode_type { AlphaISA::mode_kernel = 0, AlphaISA::mode_executive = 1, AlphaISA::mode_supervisor = 2, AlphaISA::mode_user = 3, AlphaISA::mode_number }

Functions
StaticInstPtr	AlphaISA::decodeInst (ExtMachInst)

Variables
const Addr	AlphaISA::PageShift = 13

const Addr	AlphaISA::PageBytes = ULL(1) << PageShift

const Addr	AlphaISA::PageMask = ~(PageBytes - 1)

const Addr	AlphaISA::PageOffset = PageBytes - 1

const Addr	AlphaISA::PteShift = 3

const Addr	AlphaISA::NPtePageShift = PageShift - PteShift

const Addr	AlphaISA::NPtePage = ULL(1) << NPtePageShift

const Addr	AlphaISA::PteMask = NPtePage - 1

const Addr	AlphaISA::USegBase = ULL(0x0)

const Addr	AlphaISA::USegEnd = ULL(0x000003ffffffffff)

const Addr	AlphaISA::K0SegBase = ULL(0xfffffc0000000000)

const Addr	AlphaISA::K0SegEnd = ULL(0xfffffdffffffffff)

const Addr	AlphaISA::K1SegBase = ULL(0xfffffe0000000000)

const Addr	AlphaISA::K1SegEnd = ULL(0xffffffffffffffff)

const int	AlphaISA::MachineBytes = 8

const ExtMachInst	AlphaISA::NoopMachInst = 0x2ffe0000

const bool	AlphaISA::HasUnalignedMemAcc = false

const bool	AlphaISA::CurThreadInfoImplemented = true

const int	AlphaISA::CurThreadInfoReg = AlphaISA::IPR_PALtemp23

Macro Definition Documentation

#define ISA_HAS_DELAY_SLOT 0

Definition at line 49 of file isa_traits.hh.

Namespaces