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EventBase Class Reference

Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions. More...

#include <eventq.hh>

Inheritance diagram for EventBase:
BaseGlobalEvent Event BaseGlobalEventTemplate< Derived > BaseGlobalEventTemplate< GlobalEvent > BaseGlobalEventTemplate< GlobalSyncEvent > AtomicSimpleCPU::TickEvent BaseGlobalEvent::BarrierEvent BaseKvmCPU::TickEvent BasePixelPump::PixelEvent BaseRemoteGDB::SingleStepEvent BaseRemoteGDB::TrapEvent ComputeUnit::DataPort::MemReqEvent ComputeUnit::DataPort::MemRespEvent Consumer::ConsumerEvent CountedExitEvent CpuEvent DefaultCommit< Impl >::TrapEvent DefaultFetch< Impl >::FinishTranslationEvent DmaCallback::DmaChunkEvent DmaReadFifo::DmaDoneEvent DVFSHandler::UpdateEvent EndQuiesceEvent EtherBus::DoneEvent EtherTapBase::TxEvent EventWrapper< T, F > EventWrapper< ArchTimer,&ArchTimer::counterLimitReached > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL0LongDescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL1DescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL1LongDescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL2DescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL2LongDescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL3LongDescriptorWrapper > EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::processWalkWrapper > EventWrapper< BaseCache::CacheSlavePort,&BaseCache::CacheSlavePort::processSendRetry > EventWrapper< BaseXBar::Layer,&BaseXBar::Layer::releaseLayer > EventWrapper< Bridge::BridgeMasterPort,&Bridge::BridgeMasterPort::trySendTiming > EventWrapper< Bridge::BridgeSlavePort,&Bridge::BridgeSlavePort::trySendTiming > EventWrapper< Cache,&Cache::writebackTempBlockAtomic > EventWrapper< CommMonitor,&CommMonitor::samplePeriodic > EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::fetchAddrComplete > EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::fetchDescComplete > EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::readCopyBytesComplete > EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::writeCopyBytesComplete > EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::writeStatusComplete > EventWrapper< CpuLocalTimer::Timer,&CpuLocalTimer::Timer::timerAtZero > EventWrapper< CpuLocalTimer::Timer,&CpuLocalTimer::Timer::watchdogAtZero > EventWrapper< Device,&Device::txEventTransmit > EventWrapper< DmaPort,&DmaPort::sendDma > EventWrapper< DRAMCtrl,&DRAMCtrl::processNextReqEvent > EventWrapper< DRAMCtrl,&DRAMCtrl::processRespondEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processActivateEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processPowerEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processPrechargeEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processRefreshEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processWakeUpEvent > EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processWriteDoneEvent > EventWrapper< DRAMSim2,&DRAMSim2::sendResponse > EventWrapper< DRAMSim2,&DRAMSim2::tick > EventWrapper< ElasticTrace,&ElasticTrace::regEtraceListeners > EventWrapper< EnergyCtrl,&EnergyCtrl::updatePLAck > EventWrapper< EtherSwitch::Interface,&EtherSwitch::Interface::transmit > EventWrapper< FlashDevice,&FlashDevice::actionComplete > EventWrapper< HDLcd,&HDLcd::virtRefresh > EventWrapper< IdeDisk,&IdeDisk::dmaPrdReadDone > EventWrapper< IdeDisk,&IdeDisk::dmaReadDone > EventWrapper< IdeDisk,&IdeDisk::dmaWriteDone > EventWrapper< IdeDisk,&IdeDisk::doDmaRead > EventWrapper< IdeDisk,&IdeDisk::doDmaTransfer > EventWrapper< IdeDisk,&IdeDisk::doDmaWrite > EventWrapper< IGbE,&IGbE::delayIntEvent > EventWrapper< IGbE,&IGbE::radvProcess > EventWrapper< IGbE,&IGbE::rdtrProcess > EventWrapper< IGbE,&IGbE::tadvProcess > EventWrapper< IGbE,&IGbE::tick > EventWrapper< IGbE,&IGbE::tidvProcess > EventWrapper< IGbE::DescCache,&IGbE::DescCache::fetchComplete > EventWrapper< IGbE::DescCache,&IGbE::DescCache::fetchDescriptors1 > EventWrapper< IGbE::DescCache,&IGbE::DescCache::wbComplete > EventWrapper< IGbE::DescCache,&IGbE::DescCache::writeback1 > EventWrapper< IGbE::RxDescCache,&IGbE::RxDescCache::pktComplete > EventWrapper< IGbE::RxDescCache,&IGbE::RxDescCache::pktSplitDone > EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::headerComplete > EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::nullCallback > EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::pktComplete > EventWrapper< Link,&Link::processTxQueue > EventWrapper< Link,&Link::txDone > EventWrapper< MasterPort,&MasterPort::sendRetryResp > EventWrapper< MemTest,&MemTest::noRequest > EventWrapper< MemTest,&MemTest::noResponse > EventWrapper< MemTest,&MemTest::tick > EventWrapper< NSGigE,&NSGigE::rxDmaReadDone > EventWrapper< NSGigE,&NSGigE::rxDmaWriteDone > EventWrapper< NSGigE,&NSGigE::rxKick > EventWrapper< NSGigE,&NSGigE::txDmaReadDone > EventWrapper< NSGigE,&NSGigE::txDmaWriteDone > EventWrapper< NSGigE,&NSGigE::txEventTransmit > EventWrapper< NSGigE,&NSGigE::txKick > EventWrapper< PacketQueue,&PacketQueue::processSendEvent > EventWrapper< Pl011,&Pl011::generateInterrupt > EventWrapper< PL031,&PL031::counterMatch > EventWrapper< Pl050,&Pl050::generateInterrupt > EventWrapper< Pl111,&Pl111::fillFifo > EventWrapper< Pl111,&Pl111::generateInterrupt > EventWrapper< Pl111,&Pl111::readFramebuffer > EventWrapper< Root,&Root::timeSync > EventWrapper< RxLink,&RxLink::rxDone > EventWrapper< SerialLink::SerialLinkMasterPort,&SerialLink::SerialLinkMasterPort::trySendTiming > EventWrapper< SerialLink::SerialLinkSlavePort,&SerialLink::SerialLinkSlavePort::trySendTiming > EventWrapper< SimpleMemory,&SimpleMemory::dequeue > EventWrapper< SimpleMemory,&SimpleMemory::release > EventWrapper< Sinic::Device,&Sinic::Device::rxDmaDone > EventWrapper< Sinic::Device,&Sinic::Device::txDmaDone > EventWrapper< Sp804::Timer,&Sp804::Timer::counterAtZero > EventWrapper< ThermalModel,&ThermalModel::doStep > EventWrapper< TimingSimpleCPU,&TimingSimpleCPU::fetch > EventWrapper< TraceCPU,&TraceCPU::schedDcacheNext > EventWrapper< TraceCPU,&TraceCPU::schedIcacheNext > EventWrapper< TrafficGen,&TrafficGen::noProgress > EventWrapper< TrafficGen,&TrafficGen::update > EventWrapper< TxLink,&TxLink::txDone > EventWrapper< UFSHostDevice,&UFSHostDevice::finalUTP > EventWrapper< UFSHostDevice,&UFSHostDevice::readDone > EventWrapper< UFSHostDevice,&UFSHostDevice::readGarbage > EventWrapper< UFSHostDevice,&UFSHostDevice::SCSIStart > EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::taskStart > EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::transferStart > EventWrapper< UFSHostDevice,&UFSHostDevice::writeDone > EventWrapper< X86ISA::GpuTLB,&X86ISA::GpuTLB::cleanup > EventWrapper< X86ISA::GpuTLB,&X86ISA::GpuTLB::exitCallback > EventWrapper< X86ISA::Walker,&X86ISA::Walker::startWalkWrapper > FullO3CPU< Impl >::TickEvent GarnetSyntheticTraffic::TickEvent GPUCoalescer::GPUCoalescerWakeupEvent GPUCoalescer::IssueEvent GpuDispatcher::TickEvent InstructionQueue< Impl >::FUCompletion Intel8254Timer::Counter::CounterEvent LdsState::TickEvent LocalSimLoopExitEvent LSQUnit< Impl >::WritebackEvent MC146818::RTCEvent MC146818::RTCTickEvent Minor::LSQ::SplitDataRequest::TranslationEvent MipsISA::ISA::CP0Event Pl390::PostIntEvent PyEvent RubyDirectedTester::DirectedStartEvent RubySystem::RubyEvent RubyTester::CheckStartEvent Sequencer::SequencerWakeupEvent Shader::TickEvent StubSlavePort::ResponseEvent Ticked::ClockEvent TimingSimpleCPU::IprEvent TimingSimpleCPU::TimingCPUPort::TickEvent TLBCoalescer::CleanupEvent TLBCoalescer::IssueProbeEvent Uart8250::IntrEvent VGic::PostVIntEvent X86ISA::GpuTLB::TLBEvent

Public Types

typedef int8_t Priority
 

Static Public Attributes

static const Priority Minimum_Pri = SCHAR_MIN
 Event priorities, to provide tie-breakers for events scheduled at the same cycle. More...
 
static const Priority Debug_Enable_Pri = -101
 If we enable tracing on a particular cycle, do that as the very first thing so we don't miss any of the events on that cycle (even if we enter the debugger). More...
 
static const Priority Debug_Break_Pri = -100
 Breakpoints should happen before anything else (except enabling trace output), so we don't miss any action when debugging. More...
 
static const Priority CPU_Switch_Pri = -31
 CPU switches schedule the new CPU's tick event for the same cycle (after unscheduling the old CPU's tick event). More...
 
static const Priority Delayed_Writeback_Pri = -1
 For some reason "delayed" inter-cluster writebacks are scheduled before regular writebacks (which have default priority). More...
 
static const Priority Default_Pri = 0
 Default is zero for historical reasons. More...
 
static const Priority DVFS_Update_Pri = 31
 DVFS update event leads to stats dump therefore given a lower priority to ensure all relevant states have been updated. More...
 
static const Priority Serialize_Pri = 32
 Serailization needs to occur before tick events also, so that a serialize/unserialize is identical to an on-line CPU switch. More...
 
static const Priority CPU_Tick_Pri = 50
 CPU ticks must come after other associated CPU events (such as writebacks). More...
 
static const Priority Stat_Event_Pri = 90
 Statistics events (dump, reset, etc.) come after everything else, but before exit. More...
 
static const Priority Progress_Event_Pri = 95
 Progress events come at the end. More...
 
static const Priority Sim_Exit_Pri = 100
 If we want to exit on this cycle, it's the very last thing we do. More...
 
static const Priority Maximum_Pri = SCHAR_MAX
 Maximum priority. More...
 

Protected Types

typedef unsigned short FlagsType
 
typedef ::Flags< FlagsTypeFlags
 

Static Protected Attributes

static const FlagsType PublicRead = 0x003f
 
static const FlagsType PublicWrite = 0x001d
 
static const FlagsType Squashed = 0x0001
 
static const FlagsType Scheduled = 0x0002
 
static const FlagsType Managed = 0x0004
 
static const FlagsType AutoDelete = Managed
 
static const FlagsType Reserved0 = 0x0008
 This used to be AutoSerialize. More...
 
static const FlagsType IsExitEvent = 0x0010
 
static const FlagsType IsMainQueue = 0x0020
 
static const FlagsType Initialized = 0x7a40
 
static const FlagsType InitMask = 0xffc0
 

Detailed Description

Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions.

This class should not be used directly.

Definition at line 92 of file eventq.hh.

Member Typedef Documentation

typedef ::Flags<FlagsType> EventBase::Flags
protected

Definition at line 96 of file eventq.hh.

typedef unsigned short EventBase::FlagsType
protected

Definition at line 95 of file eventq.hh.

typedef int8_t EventBase::Priority

Definition at line 116 of file eventq.hh.

Member Data Documentation

const FlagsType EventBase::AutoDelete = Managed
staticprotected
const Priority EventBase::CPU_Switch_Pri = -31
static

CPU switches schedule the new CPU's tick event for the same cycle (after unscheduling the old CPU's tick event).

The switch needs to come before any tick events to make sure we don't tick both CPUs in the same cycle.

Definition at line 140 of file eventq.hh.

const Priority EventBase::CPU_Tick_Pri = 50
static

CPU ticks must come after other associated CPU events (such as writebacks).

Definition at line 161 of file eventq.hh.

const Priority EventBase::Debug_Break_Pri = -100
static

Breakpoints should happen before anything else (except enabling trace output), so we don't miss any action when debugging.

Definition at line 134 of file eventq.hh.

const Priority EventBase::Debug_Enable_Pri = -101
static

If we enable tracing on a particular cycle, do that as the very first thing so we don't miss any of the events on that cycle (even if we enter the debugger).

Definition at line 129 of file eventq.hh.

const Priority EventBase::Default_Pri = 0
static

Default is zero for historical reasons.

Definition at line 148 of file eventq.hh.

Referenced by pybind_init_event().

const Priority EventBase::Delayed_Writeback_Pri = -1
static

For some reason "delayed" inter-cluster writebacks are scheduled before regular writebacks (which have default priority).

Steve?

Definition at line 145 of file eventq.hh.

const Priority EventBase::DVFS_Update_Pri = 31
static

DVFS update event leads to stats dump therefore given a lower priority to ensure all relevant states have been updated.

Definition at line 152 of file eventq.hh.

const FlagsType EventBase::Initialized = 0x7a40
staticprotected

Definition at line 112 of file eventq.hh.

Referenced by Event::initialized().

const FlagsType EventBase::InitMask = 0xffc0
staticprotected

Definition at line 113 of file eventq.hh.

Referenced by Event::initialized().

const FlagsType EventBase::IsExitEvent = 0x0010
staticprotected

Definition at line 110 of file eventq.hh.

Referenced by Event::isExitEvent().

const FlagsType EventBase::IsMainQueue = 0x0020
staticprotected

Definition at line 111 of file eventq.hh.

Referenced by EventQueue::serviceOne().

const FlagsType EventBase::Managed = 0x0004
staticprotected
const Priority EventBase::Maximum_Pri = SCHAR_MAX
static

Maximum priority.

Definition at line 175 of file eventq.hh.

const Priority EventBase::Minimum_Pri = SCHAR_MIN
static

Event priorities, to provide tie-breakers for events scheduled at the same cycle.

Most events are scheduled at the default priority; these values are used to control events that need to be ordered within a cycle. Minimum priority

Definition at line 124 of file eventq.hh.

const Priority EventBase::Progress_Event_Pri = 95
static

Progress events come at the end.

Definition at line 168 of file eventq.hh.

Referenced by simulate().

const FlagsType EventBase::PublicRead = 0x003f
staticprotected

Definition at line 98 of file eventq.hh.

Referenced by Event::getFlags(), and Event::isFlagSet().

const FlagsType EventBase::PublicWrite = 0x001d
staticprotected

Definition at line 99 of file eventq.hh.

Referenced by Event::clearFlags(), Event::Event(), and Event::setFlags().

const FlagsType EventBase::Reserved0 = 0x0008
staticprotected

This used to be AutoSerialize.

This value can't be reused without changing the checkpoint version since the flag field gets serialized.

Definition at line 109 of file eventq.hh.

const FlagsType EventBase::Scheduled = 0x0002
staticprotected
const Priority EventBase::Serialize_Pri = 32
static

Serailization needs to occur before tick events also, so that a serialize/unserialize is identical to an on-line CPU switch.

Definition at line 157 of file eventq.hh.

const Priority EventBase::Sim_Exit_Pri = 100
static

If we want to exit on this cycle, it's the very last thing we do.

Definition at line 172 of file eventq.hh.

const FlagsType EventBase::Squashed = 0x0001
staticprotected
const Priority EventBase::Stat_Event_Pri = 90
static

Statistics events (dump, reset, etc.) come after everything else, but before exit.

Definition at line 165 of file eventq.hh.


The documentation for this class was generated from the following file:

Generated on Fri Jun 9 2017 13:04:10 for gem5 by doxygen 1.8.6