The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model. More...

#include <trace_cpu.hh>

Inheritance diagram for TraceCPU:

Classes
class	DcachePort
	DcachePort class that interfaces with L1 Data Cache. More...

class	ElasticDataGen
	The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies. More...

class	FixedRetryGen
	Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests. More...

class	IcachePort
	IcachePort class that interfaces with L1 Instruction Cache. More...

Public Member Functions
	TraceCPU (TraceCPUParams *params)

	~TraceCPU ()

void	init ()

Counter	totalInsts () const
	This is a pure virtual function in BaseCPU. More...

Counter	totalOps () const
	Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay. More...

void	updateNumOps (uint64_t rob_num)

void	wakeup (ThreadID tid=0)

void	takeOverFrom (BaseCPU *oldCPU)

void	icacheRetryRecvd ()
	When instruction cache port receives a retry, schedule event icacheNextEvent. More...

void	dcacheRetryRecvd ()
	When data cache port receives a retry, schedule event dcacheNextEvent. More...

void	dcacheRecvTimingResp (PacketPtr pkt)
	When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback. More...

void	schedDcacheNextEvent (Tick when)
	Schedule event dcacheNextEvent at the given tick. More...

MasterPort &	getInstPort ()
	Used to get a reference to the icache port. More...

MasterPort &	getDataPort ()
	Used to get a reference to the dcache port. More...

void	regStats ()

Protected Member Functions
void	schedIcacheNext ()
	This is the control flow that uses the functionality of the icacheGen to replay the trace. More...

void	schedDcacheNext ()
	This is the control flow that uses the functionality of the dcacheGen to replay the trace. More...

void	checkAndSchedExitEvent ()
	This is called when either generator finishes executing from the trace. More...

Protected Attributes
IcachePort	icachePort
	Port to connect to L1 instruction cache. More...

DcachePort	dcachePort
	Port to connect to L1 data cache. More...

const MasterID	instMasterID
	Master id for instruction read requests. More...

const MasterID	dataMasterID
	Master id for data read and write requests. More...

std::string	instTraceFile
	File names for input instruction and data traces. More...

std::string	dataTraceFile

FixedRetryGen	icacheGen
	Instance of FixedRetryGen to replay instruction read requests. More...

ElasticDataGen	dcacheGen
	Instance of ElasticDataGen to replay data read and write requests. More...

EventWrapper< TraceCPU,&TraceCPU::schedIcacheNext >	icacheNextEvent
	Event for the control flow method schedIcacheNext() More...

EventWrapper< TraceCPU,&TraceCPU::schedDcacheNext >	dcacheNextEvent
	Event for the control flow method schedDcacheNext() More...

bool	oneTraceComplete
	Set to true when one of the generators finishes replaying its trace. More...

Tick	traceOffset
	This stores the time offset in the trace, which is taken away from the ready times of requests. More...

CountedExitEvent *	execCompleteEvent
	A CountedExitEvent which when serviced decrements the counter. More...

const bool	enableEarlyExit
	Exit when any one Trace CPU completes its execution. More...

const uint64_t	progressMsgInterval
	Interval of committed instructions specified by the user at which a progress info message is printed. More...

uint64_t	progressMsgThreshold

Stats::Scalar	numSchedDcacheEvent

Stats::Scalar	numSchedIcacheEvent

Stats::Scalar	numOps
	Stat for number of simulated micro-ops. More...

Stats::Formula	cpi
	Stat for the CPI. More...

Static Protected Attributes
static int	numTraceCPUs = 0
	Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events. More...

Additional Inherited Members
Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

Detailed Description

The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.

The elastic trace is an execution trace with register data dependencies and ordering dependencies annotated to it. The trace cpu also replays a fixed timestamp fetch trace that is also generated by the elastic trace probe. This trace cpu model aims at achieving faster simulation compared to the detailed cpu model and good correlation when the same trace is used for playback on different memory sub-systems.

The TraceCPU inherits from BaseCPU so some virtual methods need to be defined. It has two port subclasses inherited from MasterPort for instruction and data ports. It issues the memory requests deducing the timing from the trace and without performing real execution of micro-ops. As soon as the last dependency for an instruction is complete, its computational delay, also provided in the input trace is added. The dependency-free nodes are maintained in a list, called 'ReadyList', ordered by ready time. Instructions which depend on load stall until the responses for read requests are received thus achieving elastic replay. If the dependency is not found when adding a new node, it is assumed complete. Thus, if this node is found to be completely dependency-free its issue time is calculated and it is added to the ready list immediately. This is encapsulated in the subclass ElasticDataGen.

If ready nodes are issued in an unconstrained way there can be more nodes outstanding which results in divergence in timing compared to the O3CPU. Therefore, the Trace CPU also models hardware resources. A sub-class to model hardware resources contains the maximum sizes of load buffer, store buffer and ROB. If resources are not available, the node is not issued. Such nodes that are pending issue are held in the 'depFreeQueue' structure.

Modeling the ROB size in the Trace CPU as a resource limitation is arguably the most important parameter of all resources. The ROB occupancy is estimated using the newly added field 'robNum'. We need to use ROB number as sequence number is at times much higher due to squashing and trace replay is focused on correct path modeling.

A map called 'inFlightNodes' is added to track nodes that are not only in the readyList but also load nodes that are executed (and thus removed from readyList) but are not complete. ReadyList handles what and when to execute next node while the inFlightNodes is used for resource modelling. The oldest ROB number is updated when any node occupies the ROB or when an entry in the ROB is released. The ROB occupancy is equal to the difference in the ROB number of the newly dependency-free node and the oldest ROB number in flight.

If no node depends on a non load/store node then there is no reason to track it in the dependency graph. We filter out such nodes but count them and add a weight field to the subsequent node that we do include in the trace. The weight field is used to model ROB occupancy during replay.

The depFreeQueue is chosen to be FIFO so that child nodes which are in program order get pushed into it in that order and thus issued in program order, like in the O3CPU. This is also why the dependents is made a sequential container, std::set to std::vector. We only check head of the depFreeQueue as nodes are issued in order and blocking on head models that better than looping the entire queue. An alternative choice would be to inspect top N pending nodes where N is the issue-width. This is left for future as the timing correlation looks good as it is.

At the start of an execution event, first we attempt to issue such pending nodes by checking if appropriate resources have become available. If yes, we compute the execute tick with respect to the time then. Then we proceed to complete nodes from the readyList.

When a read response is received, sometimes a dependency on it that was supposed to be released when it was issued is still not released. This occurs because the dependent gets added to the graph after the read was sent. So the check is made less strict and the dependency is marked complete on read response instead of insisting that it should have been removed on read sent.

There is a check for requests spanning two cache lines as this condition triggers an assert fail in the L1 cache. If it does then truncate the size to access only until the end of that line and ignore the remainder. Strictly-ordered requests are skipped and the dependencies on such requests are handled by simply marking them complete immediately.

A CountedExitEvent that contains a static int belonging to the Trace CPU class as a down counter is used to implement multi Trace CPU simulation exit.

Definition at line 144 of file trace_cpu.hh.

Constructor & Destructor Documentation

TraceCPU::TraceCPU ( TraceCPUParams * params )

Definition at line 49 of file trace_cpu.cc.

References fatal_if(), and numTraceCPUs.

TraceCPU::~TraceCPU ( )

Definition at line 84 of file trace_cpu.cc.

Member Function Documentation

void TraceCPU::checkAndSchedExitEvent ( )

protected

This is called when either generator finishes executing from the trace.

Definition at line 205 of file trace_cpu.cc.

References curTick(), enableEarlyExit, execCompleteEvent, exitSimLoop(), inform, name(), and oneTraceComplete.

Referenced by schedDcacheNext(), and schedIcacheNext().

void TraceCPU::dcacheRecvTimingResp ( PacketPtr pkt )

When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback.

Parameters

pkt	Pointer to packet received

Definition at line 1241 of file trace_cpu.cc.

References TraceCPU::ElasticDataGen::completeMemAccess(), dcacheGen, and DPRINTF.

Referenced by TraceCPU::DcachePort::recvTimingResp().

void TraceCPU::dcacheRetryRecvd ( )

When data cache port receives a retry, schedule event dcacheNextEvent.

Definition at line 1198 of file trace_cpu.cc.

References curTick(), dcacheNextEvent, and DPRINTF.

Referenced by TraceCPU::DcachePort::recvReqRetry().

MasterPort& TraceCPU::getDataPort ( )

inline

Used to get a reference to the dcache port.

Definition at line 1152 of file trace_cpu.hh.

References dcachePort.

Referenced by takeOverFrom().

MasterPort& TraceCPU::getInstPort ( )

inline

Used to get a reference to the icache port.

Definition at line 1149 of file trace_cpu.hh.

References icachePort.

Referenced by takeOverFrom().

void TraceCPU::icacheRetryRecvd ( )

When instruction cache port receives a retry, schedule event icacheNextEvent.

Definition at line 1188 of file trace_cpu.cc.

References curTick(), DPRINTF, and icacheNextEvent.

Referenced by TraceCPU::IcachePort::recvReqRetry().

void TraceCPU::init ( )

Definition at line 123 of file trace_cpu.cc.

References TraceCPU::ElasticDataGen::adjustInitTraceOffset(), dataTraceFile, dcacheGen, dcacheNextEvent, DPRINTF, enableEarlyExit, execCompleteEvent, icacheGen, icacheNextEvent, inform, Stats::init, TraceCPU::FixedRetryGen::init(), TraceCPU::ElasticDataGen::init(), instTraceFile, name(), numTraceCPUs, and traceOffset.

void TraceCPU::regStats ( )

Definition at line 226 of file trace_cpu.cc.

References cpi, dcacheGen, Stats::DataWrap< Derived, InfoProxyType >::desc(), icacheGen, name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numOps, numSchedDcacheEvent, numSchedIcacheEvent, Stats::DataWrap< Derived, InfoProxyType >::precision(), TraceCPU::FixedRetryGen::regStats(), and TraceCPU::ElasticDataGen::regStats().

void TraceCPU::schedDcacheNext ( )

protected

This is the control flow that uses the functionality of the dcacheGen to replay the trace.

It calls execute(). It checks if execution is complete and schedules an event to exit simulation accordingly.

Definition at line 191 of file trace_cpu.cc.

References checkAndSchedExitEvent(), dcacheGen, DPRINTF, TraceCPU::ElasticDataGen::execute(), and TraceCPU::ElasticDataGen::isExecComplete().

void TraceCPU::schedDcacheNextEvent ( Tick when )

Schedule event dcacheNextEvent at the given tick.

Parameters

when	Tick at which to schedule event

Definition at line 1208 of file trace_cpu.cc.

References dcacheNextEvent, DPRINTF, numSchedDcacheEvent, Event::scheduled(), and Event::when().

Referenced by TraceCPU::ElasticDataGen::completeMemAccess(), and TraceCPU::ElasticDataGen::execute().

void TraceCPU::schedIcacheNext ( )

protected

This is the control flow that uses the functionality of the icacheGen to replay the trace.

It calls tryNext(). If it returns true then next event is scheduled at curTick() plus delta. If it returns false then delta is ignored and control is brought back via recvRetry().

Definition at line 166 of file trace_cpu.cc.

References checkAndSchedExitEvent(), curTick(), DPRINTF, icacheGen, icacheNextEvent, TraceCPU::FixedRetryGen::isTraceComplete(), numSchedIcacheEvent, TraceCPU::FixedRetryGen::tickDelta(), and TraceCPU::FixedRetryGen::tryNext().

void TraceCPU::takeOverFrom ( BaseCPU * oldCPU )

Definition at line 106 of file trace_cpu.cc.

References MasterPort::bind(), getDataPort(), and getInstPort().

Counter TraceCPU::totalInsts ( ) const

inline

This is a pure virtual function in BaseCPU.

As we don't know how many insts are in the trace but only know how how many micro-ops are we cannot count this stat.

Returns: 0

Definition at line 160 of file trace_cpu.hh.

Counter TraceCPU::totalOps ( ) const

inline

Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay.

Returns: number of micro-ops i.e. nodes in the elastic data generator

Definition at line 171 of file trace_cpu.hh.

References numOps, and Stats::ScalarBase< Derived, Stor >::value().

void TraceCPU::updateNumOps ( uint64_t rob_num )

Definition at line 96 of file trace_cpu.cc.

References inform, name(), numOps, progressMsgInterval, progressMsgThreshold, and Stats::ScalarBase< Derived, Stor >::value().

Referenced by TraceCPU::ElasticDataGen::completeMemAccess(), and TraceCPU::ElasticDataGen::execute().

void TraceCPU::wakeup ( ThreadID tid = 0 )

inline

Definition at line 183 of file trace_cpu.hh.

Member Data Documentation

Stats::Formula TraceCPU::cpi

protected

Stat for the CPI.

This is really cycles per micro-op and not inst.

Definition at line 1144 of file trace_cpu.hh.

Referenced by regStats().

const MasterID TraceCPU::dataMasterID

protected

Master id for data read and write requests.

Definition at line 332 of file trace_cpu.hh.

std::string TraceCPU::dataTraceFile

protected

Definition at line 335 of file trace_cpu.hh.

Referenced by init().

ElasticDataGen TraceCPU::dcacheGen

protected

Instance of ElasticDataGen to replay data read and write requests.

Definition at line 1067 of file trace_cpu.hh.

Referenced by dcacheRecvTimingResp(), init(), regStats(), and schedDcacheNext().

EventWrapper<TraceCPU, &TraceCPU::schedDcacheNext> TraceCPU::dcacheNextEvent

protected

Event for the control flow method schedDcacheNext()

Definition at line 1088 of file trace_cpu.hh.

Referenced by dcacheRetryRecvd(), init(), and schedDcacheNextEvent().

DcachePort TraceCPU::dcachePort

protected

Port to connect to L1 data cache.

Definition at line 326 of file trace_cpu.hh.

Referenced by getDataPort().

const bool TraceCPU::enableEarlyExit

protected

Exit when any one Trace CPU completes its execution.

If this is configured true then the execCompleteEvent is not scheduled.

Definition at line 1123 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

CountedExitEvent* TraceCPU::execCompleteEvent

protected

A CountedExitEvent which when serviced decrements the counter.

A sim exit event is scheduled when the counter equals zero, that is all instances of Trace CPU have had their execCompleteEvent serviced.

Definition at line 1117 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

FixedRetryGen TraceCPU::icacheGen

protected

Instance of FixedRetryGen to replay instruction read requests.

Definition at line 1064 of file trace_cpu.hh.

Referenced by init(), regStats(), and schedIcacheNext().

EventWrapper<TraceCPU, &TraceCPU::schedIcacheNext> TraceCPU::icacheNextEvent

protected

Event for the control flow method schedIcacheNext()

Definition at line 1085 of file trace_cpu.hh.

Referenced by icacheRetryRecvd(), init(), and schedIcacheNext().

IcachePort TraceCPU::icachePort

protected

Port to connect to L1 instruction cache.

Definition at line 323 of file trace_cpu.hh.

Referenced by getInstPort().

const MasterID TraceCPU::instMasterID

protected

Master id for instruction read requests.

Definition at line 329 of file trace_cpu.hh.

std::string TraceCPU::instTraceFile

protected

File names for input instruction and data traces.

Definition at line 335 of file trace_cpu.hh.

Referenced by init().

Stats::Scalar TraceCPU::numOps

protected

Stat for number of simulated micro-ops.

Definition at line 1142 of file trace_cpu.hh.

Referenced by regStats(), totalOps(), and updateNumOps().

Stats::Scalar TraceCPU::numSchedDcacheEvent

protected

Definition at line 1138 of file trace_cpu.hh.

Referenced by regStats(), and schedDcacheNextEvent().

Stats::Scalar TraceCPU::numSchedIcacheEvent

protected

Definition at line 1139 of file trace_cpu.hh.

Referenced by regStats(), and schedIcacheNext().

int TraceCPU::numTraceCPUs = 0

staticprotected

Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events.

It is incremented in the constructor call so that the total is arrived at automatically.

Definition at line 1110 of file trace_cpu.hh.

Referenced by init(), and TraceCPU().

bool TraceCPU::oneTraceComplete

protected

Set to true when one of the generators finishes replaying its trace.

Definition at line 1094 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent().

const uint64_t TraceCPU::progressMsgInterval

protected

Interval of committed instructions specified by the user at which a progress info message is printed.

Definition at line 1129 of file trace_cpu.hh.

Referenced by updateNumOps().

uint64_t TraceCPU::progressMsgThreshold

protected

Definition at line 1136 of file trace_cpu.hh.

Referenced by updateNumOps().

Tick TraceCPU::traceOffset

protected

This stores the time offset in the trace, which is taken away from the ready times of requests.

This is specially useful because the time offset can be very large if the traces are generated from the middle of a program.

Definition at line 1102 of file trace_cpu.hh.

Referenced by init().

The documentation for this class was generated from the following files:

cpu/trace/trace_cpu.hh
cpu/trace/trace_cpu.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Static Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Member Data Documentation