commit.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2010-2012, 2014 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Kevin Lim
 *          Korey Sewell
 */

#ifndef __CPU_O3_COMMIT_HH__
#define __CPU_O3_COMMIT_HH__

#include <queue>

#include "base/statistics.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
#include "sim/probe/probe.hh"

struct DerivO3CPUParams;

template <class>
struct O3ThreadState;

template<class Impl>
class DefaultCommit
{
  public:
    // Typedefs from the Impl.
    typedef typename Impl::O3CPU O3CPU;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::CPUPol CPUPol;

    typedef typename CPUPol::RenameMap RenameMap;
    typedef typename CPUPol::ROB ROB;

    typedef typename CPUPol::TimeStruct TimeStruct;
    typedef typename CPUPol::FetchStruct FetchStruct;
    typedef typename CPUPol::IEWStruct IEWStruct;
    typedef typename CPUPol::RenameStruct RenameStruct;

    typedef typename CPUPol::Fetch Fetch;
    typedef typename CPUPol::IEW IEW;

    typedef O3ThreadState<Impl> Thread;

    class TrapEvent : public Event {
      private:
        DefaultCommit<Impl> *commit;
        ThreadID tid;

      public:
        TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);

        void process();
        const char *description() const;
    };

    enum CommitStatus{
        Active,
        Inactive
    };

    enum ThreadStatus {
        Running,
        Idle,
        ROBSquashing,
        TrapPending,
        FetchTrapPending,
        SquashAfterPending, //< Committing instructions before a squash.
    };

    enum CommitPolicy {
        Aggressive,
        RoundRobin,
        OldestReady
    };

  private:
    CommitStatus _status;
    CommitStatus _nextStatus;
    ThreadStatus commitStatus[Impl::MaxThreads];
    CommitPolicy commitPolicy;

    ProbePointArg<DynInstPtr> *ppCommit;
    ProbePointArg<DynInstPtr> *ppCommitStall;
    ProbePointArg<DynInstPtr> *ppSquash;

  public:
    DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);

    std::string name() const;

    void regStats();

    void regProbePoints();

    void setThreads(std::vector<Thread *> &threads);

    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);

    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);

    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);

    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);

    void setIEWStage(IEW *iew_stage);

    IEW *iewStage;

    void setActiveThreads(std::list<ThreadID> *at_ptr);

    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);

    void setROB(ROB *rob_ptr);

    void startupStage();

    void drain();

    void drainResume();

    void drainSanityCheck() const;

    bool isDrained() const;

    void takeOverFrom();

    void deactivateThread(ThreadID tid);

    void tick();

    void commit();

    size_t numROBFreeEntries(ThreadID tid);

    void generateTrapEvent(ThreadID tid, Fault inst_fault);

    void generateTCEvent(ThreadID tid);

  private:
    void updateStatus();

    bool changedROBEntries();

    void squashAll(ThreadID tid);

    void squashFromTrap(ThreadID tid);

    void squashFromTC(ThreadID tid);

    void squashFromSquashAfter(ThreadID tid);

    void squashAfter(ThreadID tid, DynInstPtr &head_inst);

    void handleInterrupt();

    void propagateInterrupt();

    void commitInsts();

    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);

    void getInsts();

    void markCompletedInsts();

    ThreadID getCommittingThread();

    ThreadID roundRobin();

    ThreadID oldestReady();

  public:
    TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }

    void pcState(const TheISA::PCState &val, ThreadID tid)
    { pc[tid] = val; }

    Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }

    Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }

    Addr microPC(ThreadID tid) { return pc[tid].microPC(); }

  private:
    TimeBuffer<TimeStruct> *timeBuffer;

    typename TimeBuffer<TimeStruct>::wire toIEW;

    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;

    TimeBuffer<FetchStruct> *fetchQueue;

    typename TimeBuffer<FetchStruct>::wire fromFetch;

    TimeBuffer<IEWStruct> *iewQueue;

    typename TimeBuffer<IEWStruct>::wire fromIEW;

    TimeBuffer<RenameStruct> *renameQueue;

    typename TimeBuffer<RenameStruct>::wire fromRename;

  public:
    ROB *rob;

  private:
    O3CPU *cpu;

    std::vector<Thread *> thread;

    bool wroteToTimeBuffer;

    bool changedROBNumEntries[Impl::MaxThreads];

    bool trapSquash[Impl::MaxThreads];

    bool tcSquash[Impl::MaxThreads];

    DynInstPtr squashAfterInst[Impl::MaxThreads];

    std::list<ThreadID> priority_list;

    const Cycles iewToCommitDelay;

    const Cycles commitToIEWDelay;

    const Cycles renameToROBDelay;

    const Cycles fetchToCommitDelay;

    const unsigned renameWidth;

    const unsigned commitWidth;

    unsigned numRobs;

    const ThreadID numThreads;

    bool drainPending;

    bool drainImminent;

    const Cycles trapLatency;

    Fault interrupt;

    TheISA::PCState pc[Impl::MaxThreads];

    InstSeqNum youngestSeqNum[Impl::MaxThreads];

    InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];

    bool trapInFlight[Impl::MaxThreads];

    bool committedStores[Impl::MaxThreads];

    bool checkEmptyROB[Impl::MaxThreads];

    std::list<ThreadID> *activeThreads;

    RenameMap *renameMap[Impl::MaxThreads];

    bool canHandleInterrupts;

    bool avoidQuiesceLiveLock;

    void updateComInstStats(DynInstPtr &inst);

    Stats::Scalar commitSquashedInsts;
    Stats::Scalar commitNonSpecStalls;
    Stats::Scalar branchMispredicts;
    Stats::Distribution numCommittedDist;

    Stats::Vector instsCommitted;
    Stats::Vector opsCommitted;
    Stats::Vector statComSwp;
    Stats::Vector statComRefs;
    Stats::Vector statComLoads;
    Stats::Vector statComMembars;
    Stats::Vector statComBranches;
    Stats::Vector statComFloating;
    Stats::Vector statComInteger;
    Stats::Vector statComFunctionCalls;
    Stats::Vector2d statCommittedInstType;

    Stats::Scalar commitEligibleSamples;
};

#endif // __CPU_O3_COMMIT_HH__