compute_unit.hh File Reference

#include <deque>
#include <map>
#include <unordered_map>
#include <vector>
#include "base/callback.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "enums/PrefetchType.hh"
#include "gpu-compute/exec_stage.hh"
#include "gpu-compute/fetch_stage.hh"
#include "gpu-compute/global_memory_pipeline.hh"
#include "gpu-compute/local_memory_pipeline.hh"
#include "gpu-compute/qstruct.hh"
#include "gpu-compute/schedule_stage.hh"
#include "gpu-compute/scoreboard_check_stage.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"

Go to the source code of this file.

Classes
class	ComputeUnit
class	ComputeUnit::CUExitCallback
class	ComputeUnit::DataPort
	Data access Port. More...
struct	ComputeUnit::DataPort::SenderState
class	ComputeUnit::DataPort::MemReqEvent
class	ComputeUnit::DataPort::MemRespEvent
class	ComputeUnit::SQCPort
struct	ComputeUnit::SQCPort::SenderState
class	ComputeUnit::DTLBPort
	Data TLB port. More...
struct	ComputeUnit::DTLBPort::SenderState
	SenderState is information carried along with the packet throughout the TLB hierarchy. More...
class	ComputeUnit::ITLBPort
struct	ComputeUnit::ITLBPort::SenderState
	SenderState is information carried along with the packet throughout the TLB hierarchy. More...
class	ComputeUnit::LDSPort
	the port intended to communicate between the CU and its LDS More...
class	ComputeUnit::LDSPort::SenderState
	SenderState is information carried along with the packet, esp. More...
class	ComputeUnit::waveIdentifier
class	ComputeUnit::waveQueue

Enumerations
enum	EXEC_POLICY { OLDEST = 0, RR }
enum	EXEC_UNIT {   SIMD0 = 0, SIMD1, SIMD2, SIMD3,   GLBMEM_PIPE, LDSMEM_PIPE, NUM_UNITS }
enum	TLB_CACHE { TLB_MISS_CACHE_MISS = 0, TLB_MISS_CACHE_HIT, TLB_HIT_CACHE_MISS, TLB_HIT_CACHE_HIT }

Variables
static const int	MAX_REGS_FOR_NON_VEC_MEM_INST = 1
static const int	MAX_WIDTH_FOR_MEM_INST = 32

Enumeration Type Documentation

enum EXEC_POLICY

Enumerator
OLDEST
RR

Definition at line 67 of file compute_unit.hh.

enum EXEC_UNIT

Enumerator
SIMD0
SIMD1
SIMD2
SIMD3
GLBMEM_PIPE
LDSMEM_PIPE
NUM_UNITS

Definition at line 74 of file compute_unit.hh.

enum TLB_CACHE

Enumerator
TLB_MISS_CACHE_MISS
TLB_MISS_CACHE_HIT
TLB_HIT_CACHE_MISS
TLB_HIT_CACHE_HIT

Definition at line 85 of file compute_unit.hh.

Variable Documentation

const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1

static

Definition at line 58 of file compute_unit.hh.

Referenced by HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), and ComputeUnit::DataPort::MemRespEvent::process().

const int MAX_WIDTH_FOR_MEM_INST = 32

static

Definition at line 59 of file compute_unit.hh.

Referenced by HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc().