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hdlcd.hh
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31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37  * Authors: Chris Emmons
38  * Andreas Sandberg
39  */
40 
41 
76 #ifndef __DEV_ARM_HDLCD_HH__
77 #define __DEV_ARM_HDLCD_HH__
78 
79 #include <fstream>
80 #include <memory>
81 
82 #include "base/bitmap.hh"
83 #include "base/framebuffer.hh"
84 #include "base/output.hh"
85 #include "dev/arm/amba_device.hh"
86 #include "dev/pixelpump.hh"
87 #include "sim/serialize.hh"
88 
89 class VncInput;
90 struct HDLcdParams;
91 class HDLcdPixelPump;
92 
93 class HDLcd: public AmbaDmaDevice
94 {
95  public:
96  HDLcd(const HDLcdParams *p);
97  ~HDLcd();
98 
99  void regStats() override;
100 
101  void serialize(CheckpointOut &cp) const override;
102  void unserialize(CheckpointIn &cp) override;
103 
104  void drainResume() override;
105 
106  public: // IO device interface
107  Tick read(PacketPtr pkt) override;
108  Tick write(PacketPtr pkt) override;
109 
110  AddrRangeList getAddrRanges() const override { return addrRanges; }
111 
112  protected: // Parameters
114  const bool workaroundSwapRB;
117  const bool enableCapture;
120 
121  protected: // Register handling
124  Version = 0x0000,
125  Int_RawStat = 0x0010,
126  Int_Clear = 0x0014,
127  Int_Mask = 0x0018,
128  Int_Status = 0x001C,
129  Fb_Base = 0x0100,
130  Fb_Line_Length = 0x0104,
131  Fb_Line_Count = 0x0108,
132  Fb_Line_Pitch = 0x010C,
133  Bus_Options = 0x0110,
134  V_Sync = 0x0200,
135  V_Back_Porch = 0x0204,
136  V_Data = 0x0208,
137  V_Front_Porch = 0x020C,
138  H_Sync = 0x0210,
139  H_Back_Porch = 0x0214,
140  H_Data = 0x0218,
141  H_Front_Porch = 0x021C,
142  Polarities = 0x0220,
143  Command = 0x0230,
144  Pixel_Format = 0x0240,
145  Red_Select = 0x0244,
146  Green_Select = 0x0248,
147  Blue_Select = 0x024C,
148  };
149 
151  static constexpr size_t BUS_OPTIONS_RESETV = 0x408;
152 
154  static constexpr size_t VERSION_RESETV = 0x1CDC0000;
155 
157  static constexpr size_t AXI_PORT_WIDTH = 8;
158 
160  static constexpr size_t MAX_BURST_LEN = 16;
161 
163  static constexpr size_t MAX_PIXEL_SIZE = 4;
164 
170  BitUnion32(VersionReg)
171  Bitfield<7,0> version_minor;
172  Bitfield<15,8> version_major;
173  Bitfield<31,16> product_id;
174  EndBitUnion(VersionReg)
175 
176  static constexpr uint32_t INT_DMA_END = (1UL << 0);
177  static constexpr uint32_t INT_BUS_ERROR = (1UL << 1);
178  static constexpr uint32_t INT_VSYNC = (1UL << 2);
179  static constexpr uint32_t INT_UNDERRUN = (1UL << 3);
180 
181  BitUnion32(FbLineCountReg)
182  Bitfield<11,0> fb_line_count;
183  Bitfield<31,12> reserved_31_12;
184  EndBitUnion(FbLineCountReg)
185 
186  BitUnion32(BusOptsReg)
187  Bitfield<4,0> burst_len;
188  Bitfield<7,5> reserved_7_5;
189  Bitfield<11,8> max_outstanding;
190  Bitfield<31,12> reserved_31_12;
191  EndBitUnion(BusOptsReg)
192 
193  BitUnion32(TimingReg)
194  Bitfield<11,0> val;
195  Bitfield<31,12> reserved_31_12;
196  EndBitUnion(TimingReg)
197 
198  BitUnion32(PolaritiesReg)
199  Bitfield<0> vsync_polarity;
200  Bitfield<1> hsync_polarity;
201  Bitfield<2> dataen_polarity;
202  Bitfield<3> data_polarity;
203  Bitfield<4> pxlclk_polarity;
204  Bitfield<31,5> reserved_31_5;
205  EndBitUnion(PolaritiesReg)
206 
208  Bitfield<0> enable;
209  Bitfield<31,1> reserved_31_1;
211 
212  BitUnion32(PixelFormatReg)
213  Bitfield<2,0> reserved_2_0;
214  Bitfield<4,3> bytes_per_pixel;
215  Bitfield<30,5> reserved_30_5;
216  Bitfield<31> big_endian;
217  EndBitUnion(PixelFormatReg)
218 
219  BitUnion32(ColorSelectReg)
220  Bitfield<4,0> offset;
221  Bitfield<7,5> reserved_7_5;
222  Bitfield<11,8> size;
223  Bitfield<15,12> reserved_15_12;
224  Bitfield<23,16> default_color;
225  Bitfield<31,24> reserved_31_24;
226  EndBitUnion(ColorSelectReg)
234  const VersionReg version;
235  uint32_t int_rawstat;
236  uint32_t int_mask;
237  uint32_t fb_base;
238  uint32_t fb_line_length;
239  FbLineCountReg fb_line_count;
240  int32_t fb_line_pitch;
241  BusOptsReg bus_options;
242  TimingReg v_sync;
243  TimingReg v_back_porch;
244  TimingReg v_data;
245  TimingReg v_front_porch;
246  TimingReg h_sync;
247  TimingReg h_back_porch;
248  TimingReg h_data;
249  TimingReg h_front_porch;
250  PolaritiesReg polarities;
252  PixelFormatReg pixel_format;
253  ColorSelectReg red_select;
254  ColorSelectReg green_select;
255  ColorSelectReg blue_select;
258  uint32_t readReg(Addr offset);
259  void writeReg(Addr offset, uint32_t value);
260 
263 
264  void createDmaEngine();
265 
266  void cmdEnable();
267  void cmdDisable();
268 
269  bool enabled() const { return command.enable; }
270 
271  public: // Pixel pump callbacks
272  bool pxlNext(Pixel &p);
273  void pxlVSyncBegin();
274  void pxlVSyncEnd();
275  void pxlUnderrun();
276  void pxlFrameDone();
277 
278  protected: // Interrupt handling
290  void setInterrupts(uint32_t ints, uint32_t mask);
291 
298  void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); }
299 
306  void intRaise(uint32_t ints) {
308  }
309 
316  void intClear(uint32_t ints) {
318  }
319 
321  uint32_t intStatus() const { return int_rawstat & int_mask; }
322 
323  protected: // Pixel output
324  class PixelPump : public BasePixelPump
325  {
326  public:
327  PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
328  : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {}
329 
330  void dumpSettings();
331 
332  protected:
333  bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
334 
335  void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
336  void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
337 
338  void onUnderrun(unsigned x, unsigned y) override {
340  }
341 
342  void onFrameDone() override { parent.pxlFrameDone(); }
343 
344  protected:
346  };
347 
349  void virtRefresh();
351 
354 
357 
360 
362 
363  protected: // DMA handling
364  class DmaEngine : public DmaReadFifo
365  {
366  public:
367  DmaEngine(HDLcd &_parent, size_t size,
368  unsigned request_size, unsigned max_pending,
369  size_t line_size, ssize_t line_pitch, unsigned num_lines);
370 
371  void startFrame(Addr fb_base);
372  void abortFrame();
373  void dumpSettings();
374 
375  void serialize(CheckpointOut &cp) const override;
376  void unserialize(CheckpointIn &cp) override;
377 
378  protected:
379  void onEndOfBlock() override;
380  void onIdle() override;
381 
383  const size_t lineSize;
384  const ssize_t linePitch;
385  const unsigned numLines;
386 
389  };
390 
391  std::unique_ptr<DmaEngine> dmaEngine;
392 
393  protected: // Statistics
394  struct {
396  } stats;
397 };
398 
399 #endif
TimingReg v_back_porch
Vertical back porch width register.
Definition: hdlcd.hh:243
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:622
Bitfield< 4 > pxlclk_polarity
Definition: hdlcd.hh:203
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:114
size_t size() const
Get the amount of data stored in the FIFO.
Definition: dma_device.hh:374
Timing generator for a pixel-based display.
Definition: pixelpump.hh:146
static constexpr size_t MAX_PIXEL_SIZE
Maximum number of bytes per pixel.
Definition: hdlcd.hh:163
Addr nextLineAddr
Definition: hdlcd.hh:387
burst_len
Definition: hdlcd.hh:187
struct HDLcd::@45 stats
bool pxlNext(Pixel &p)
Definition: hdlcd.cc:521
Bitfield< 15, 12 > reserved_15_12
Definition: hdlcd.hh:223
reserved_2_0
Definition: hdlcd.hh:213
uint32_t fb_base
Frame buffer base address register.
Definition: hdlcd.hh:237
Buffered DMA engine helper class.
Definition: dma_device.hh:315
Definition: hdlcd.hh:93
Definition: bitmap.hh:56
void onVSyncBegin() override
First pixel clock of the first VSync line.
Definition: hdlcd.hh:335
void cmdEnable()
Definition: hdlcd.cc:493
Stats::Scalar underruns
Definition: hdlcd.hh:395
TimingReg h_front_porch
Horizontal front porch width reg.
Definition: hdlcd.hh:249
Bitfield< 23, 16 > default_color
Definition: hdlcd.hh:224
const bool workaroundDmaLineCount
Definition: hdlcd.hh:115
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:613
Bitfield< 11, 8 > max_outstanding
Definition: hdlcd.hh:189
Bitfield< 30, 5 > reserved_30_5
Definition: hdlcd.hh:215
void intMask(uint32_t mask)
Convenience function to update the interrupt mask.
Definition: hdlcd.hh:298
static constexpr size_t BUS_OPTIONS_RESETV
Reset value for Bus_Options register.
Definition: hdlcd.hh:151
void pxlVSyncBegin()
Definition: hdlcd.cc:534
PixelPump pixelPump
Definition: hdlcd.hh:361
Bitfield< 7, 5 > reserved_7_5
Definition: hdlcd.hh:188
void dumpSettings()
Definition: hdlcd.cc:649
DmaEngine(HDLcd &_parent, size_t size, unsigned request_size, unsigned max_pending, size_t line_size, ssize_t line_pitch, unsigned num_lines)
Definition: hdlcd.cc:600
HDLcd & parent
Definition: hdlcd.hh:382
PixelFormatReg pixel_format
Pixel format register.
Definition: hdlcd.hh:252
Bitfield< 31, 1 > reserved_31_1
Definition: hdlcd.hh:209
const ssize_t linePitch
Definition: hdlcd.hh:384
ColorSelectReg green_select
Green color select register.
Definition: hdlcd.hh:254
ColorSelectReg blue_select
Blue color select register.
Definition: hdlcd.hh:255
CommandReg command
Command register.
Definition: hdlcd.hh:251
BusOptsReg bus_options
Bus options register.
Definition: hdlcd.hh:241
void abortFrame()
Definition: hdlcd.cc:640
Bitfield< 3 > data_polarity
Definition: hdlcd.hh:202
void onFrameDone() override
Finished displaying the visible region of a frame.
Definition: hdlcd.hh:342
const Tick virtRefreshRate
Definition: hdlcd.hh:119
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:151
HDLcd(const HDLcdParams *p)
Definition: hdlcd.cc:59
PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
Definition: hdlcd.hh:327
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2475
TimingReg v_front_porch
Vertical front porch width register.
Definition: hdlcd.hh:245
static constexpr size_t MAX_BURST_LEN
max number of beats delivered in one dma burst
Definition: hdlcd.hh:160
bool enabled() const
Definition: hdlcd.hh:269
void startFrame(Addr fb_base)
Definition: hdlcd.cc:631
version_minor
Definition: hdlcd.hh:171
Bitfield< 4, 3 > bytes_per_pixel
Definition: hdlcd.hh:214
Bitfield< 15, 8 > version_major
Definition: hdlcd.hh:172
const Addr pixelBufferSize
Definition: hdlcd.hh:118
std::unique_ptr< DmaEngine > dmaEngine
Definition: hdlcd.hh:391
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition: hdlcd.hh:356
Bitfield< 11 > enable
Definition: misc.hh:1004
TimingReg h_back_porch
Horizontal back porch width register.
Definition: hdlcd.hh:247
bool nextPixel(Pixel &p) override
Get the next pixel from the scan line buffer.
Definition: hdlcd.hh:333
Bitfield< 11, 8 > size
Definition: hdlcd.hh:222
uint32_t int_mask
Interrupt mask register.
Definition: hdlcd.hh:236
offset
Definition: hdlcd.hh:220
PixelConverter pixelConverter() const
Definition: hdlcd.cc:434
uint32_t fb_line_length
Frame buffer Line length register.
Definition: hdlcd.hh:238
This is a base class for AMBA devices that have to respond to Device and Implementer ID calls...
Bitfield< 1 > hsync_polarity
Definition: hdlcd.hh:200
uint64_t Tick
Tick count type.
Definition: types.hh:63
TimingReg h_sync
Horizontal sync width register.
Definition: hdlcd.hh:246
void intClear(uint32_t ints)
Convenience function to clear interrupts.
Definition: hdlcd.hh:316
void cmdDisable()
Definition: hdlcd.cc:509
Bitfield< 31, 24 > reserved_31_24
Definition: hdlcd.hh:225
PolaritiesReg polarities
Polarities register.
Definition: hdlcd.hh:250
PixelConverter conv
Cached pixel converter, set when the converter is enabled.
Definition: hdlcd.hh:359
STL list class.
Definition: stl.hh:54
BitUnion32(VersionReg) Bitfield<7
EndBitUnion(VersionReg) static const expr uint32_t INT_DMA_END
EventWrapper< HDLcd,&HDLcd::virtRefresh > virtRefreshEvent
Definition: hdlcd.hh:350
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:235
void dumpSettings()
Definition: hdlcd.cc:676
void setInterrupts(uint32_t ints, uint32_t mask)
Assign new interrupt values and update interrupt signals.
Definition: hdlcd.cc:586
TimingReg h_data
Horizontal data width register.
Definition: hdlcd.hh:248
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
void onIdle() override
Last response received callback.
Definition: hdlcd.cc:670
HDLcd & parent
Definition: hdlcd.hh:345
VncInput * vnc
Definition: hdlcd.hh:113
void pxlUnderrun()
Definition: hdlcd.cc:548
RegisterOffset
ARM HDLcd register offsets.
Definition: hdlcd.hh:123
static constexpr size_t VERSION_RESETV
Reset value for Version register.
Definition: hdlcd.hh:154
Bitfield< 31, 16 > product_id
Definition: hdlcd.hh:173
ColorSelectReg red_select
Red color select register.
Definition: hdlcd.hh:253
val
Definition: hdlcd.hh:194
const unsigned numLines
Definition: hdlcd.hh:385
static constexpr size_t AXI_PORT_WIDTH
AXI port width in bytes.
Definition: hdlcd.hh:157
uint32_t int_rawstat
Interrupt raw status register.
Definition: hdlcd.hh:235
void onUnderrun(unsigned x, unsigned y) override
Buffer underrun occurred on a frame.
Definition: hdlcd.hh:338
The ClockDomain provides clock to group of clocked objects bundled under the same clock domain...
Definition: clock_domain.hh:73
void virtRefresh()
Handler for fast frame refresh in KVM-mode.
Definition: hdlcd.cc:227
const size_t lineSize
Definition: hdlcd.hh:383
void pxlVSyncEnd()
Definition: hdlcd.cc:541
std::ostream CheckpointOut
Definition: serialize.hh:67
void writeReg(Addr offset, uint32_t value)
Definition: hdlcd.cc:313
int32_t fb_line_pitch
Frame buffer Line pitch register.
Definition: hdlcd.hh:240
Bitfield< 31 > big_endian
Definition: hdlcd.hh:216
void pxlFrameDone()
Definition: hdlcd.cc:557
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:255
Bitfield< 31, 12 > reserved_31_12
Definition: hdlcd.hh:183
static constexpr uint32_t INT_BUS_ERROR
Definition: hdlcd.hh:177
uint32_t readReg(Addr offset)
Definition: hdlcd.cc:274
void createDmaEngine()
Definition: hdlcd.cc:466
Bitmap bmp
Helper to write out bitmaps.
Definition: hdlcd.hh:353
static constexpr uint32_t INT_VSYNC
Definition: hdlcd.hh:178
Bitfield< 31, 5 > reserved_31_5
Definition: hdlcd.hh:204
const bool workaroundSwapRB
Definition: hdlcd.hh:114
~HDLcd()
Definition: hdlcd.cc:95
Bitfield< 2 > dataen_polarity
Definition: hdlcd.hh:201
Bitfield< 3, 0 > mask
Definition: types.hh:64
Configurable RGB pixel converter.
Definition: framebuffer.hh:91
Internal gem5 representation of a Pixel.
Definition: framebuffer.hh:58
fb_line_count
Definition: hdlcd.hh:182
void drainResume() override
Resume execution after a successful drain.
Definition: hdlcd.cc:202
DisplayTimings displayTimings() const
Definition: hdlcd.cc:457
void onVSyncEnd() override
Callback on the first pixel of the line after the end VSync region (typically the first pixel of the ...
Definition: hdlcd.hh:336
static constexpr uint32_t INT_UNDERRUN
Definition: hdlcd.hh:179
Bitfield< 0 > p
Bitfield< 1 > x
Definition: types.hh:105
const AddrRangeList addrRanges
Definition: hdlcd.hh:116
uint32_t intStatus() const
Masked interrupt status register.
Definition: hdlcd.hh:321
const bool enableCapture
Definition: hdlcd.hh:117
void intRaise(uint32_t ints)
Convenience function to raise a new interrupt.
Definition: hdlcd.hh:306
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: hdlcd.hh:110
TimingReg v_sync
Vertical sync width register.
Definition: hdlcd.hh:242
void regStats() override
Register statistics for this object.
Definition: hdlcd.cc:100
TimingReg v_data
Vertical data width register.
Definition: hdlcd.hh:244
void onEndOfBlock() override
End of block callback.
Definition: hdlcd.cc:657

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