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inst_queue.hh
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43 
44 #ifndef __CPU_O3_INST_QUEUE_HH__
45 #define __CPU_O3_INST_QUEUE_HH__
46 
47 #include <list>
48 #include <map>
49 #include <queue>
50 #include <vector>
51 
52 #include "base/statistics.hh"
53 #include "base/types.hh"
54 #include "cpu/o3/dep_graph.hh"
55 #include "cpu/inst_seq.hh"
56 #include "cpu/op_class.hh"
57 #include "cpu/timebuf.hh"
58 #include "sim/eventq.hh"
59 
60 struct DerivO3CPUParams;
61 class FUPool;
62 class MemInterface;
63 
81 template <class Impl>
83 {
84  public:
85  //Typedefs from the Impl.
86  typedef typename Impl::O3CPU O3CPU;
87  typedef typename Impl::DynInstPtr DynInstPtr;
88 
89  typedef typename Impl::CPUPol::IEW IEW;
90  typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
91  typedef typename Impl::CPUPol::IssueStruct IssueStruct;
92  typedef typename Impl::CPUPol::TimeStruct TimeStruct;
93 
94  // Typedef of iterator through the list of instructions.
96 
98  class FUCompletion : public Event {
99  private:
102 
104  int fuIdx;
105 
108 
112  bool freeFU;
113 
114  public:
116  FUCompletion(DynInstPtr &_inst, int fu_idx,
117  InstructionQueue<Impl> *iq_ptr);
118 
119  virtual void process();
120  virtual const char *description() const;
121  void setFreeFU() { freeFU = true; }
122  };
123 
125  InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
126 
129 
131  std::string name() const;
132 
134  void regStats();
135 
137  void resetState();
138 
141 
144 
147 
149  bool isDrained() const;
150 
152  void drainSanityCheck() const;
153 
155  void takeOverFrom();
156 
158  int entryAmount(ThreadID num_threads);
159 
161  void resetEntries();
162 
164  unsigned numFreeEntries();
165 
167  unsigned numFreeEntries(ThreadID tid);
168 
170  bool isFull();
171 
173  bool isFull(ThreadID tid);
174 
176  bool hasReadyInsts();
177 
179  void insert(DynInstPtr &new_inst);
180 
182  void insertNonSpec(DynInstPtr &new_inst);
183 
187  void insertBarrier(DynInstPtr &barr_inst);
188 
193 
198 
203 
209  { addToProducers(inst); }
210 
212  void processFUCompletion(DynInstPtr &inst, int fu_idx);
213 
218  void scheduleReadyInsts();
219 
221  void scheduleNonSpec(const InstSeqNum &inst);
222 
227  void commit(const InstSeqNum &inst, ThreadID tid = 0);
228 
230  int wakeDependents(DynInstPtr &completed_inst);
231 
233  void addReadyMemInst(DynInstPtr &ready_inst);
234 
239  void rescheduleMemInst(DynInstPtr &resched_inst);
240 
242  void replayMemInst(DynInstPtr &replay_inst);
243 
245  void completeMemInst(DynInstPtr &completed_inst);
246 
251  void deferMemInst(DynInstPtr &deferred_inst);
252 
254  void blockMemInst(DynInstPtr &blocked_inst);
255 
257  void cacheUnblocked();
258 
260  void violation(DynInstPtr &store, DynInstPtr &faulting_load);
261 
266  void squash(ThreadID tid);
267 
269  unsigned getCount(ThreadID tid) { return count[tid]; };
270 
272  void printInsts();
273 
274  private:
276  void doSquash(ThreadID tid);
277 
279  // Various pointers
281 
284 
286  MemInterface *dcacheInterface;
287 
290 
294  MemDepUnit memDepUnit[Impl::MaxThreads];
295 
300 
303 
306 
309 
311  // Instruction lists, ready queues, and ordering
313 
315  std::list<DynInstPtr> instList[Impl::MaxThreads];
316 
319 
324 
327 
332 
340  struct pqCompare {
341  bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
342  {
343  return lhs->seqNum > rhs->seqNum;
344  }
345  };
346 
347  typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
349 
354 
362  std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
363 
364  typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
365 
367  struct ListOrderEntry {
368  OpClass queueType;
370  };
371 
380 
382 
385 
390 
392  void addToOrderList(OpClass op_class);
393 
398  void moveToYoungerInst(ListOrderIt age_order_it);
399 
401 
403  // Various parameters
405 
407  enum IQPolicy {
411  };
412 
415 
418 
421 
423  unsigned count[Impl::MaxThreads];
424 
426  unsigned maxEntries[Impl::MaxThreads];
427 
429  unsigned freeEntries;
430 
432  unsigned numEntries;
433 
435  unsigned totalWidth;
436 
438  unsigned numPhysRegs;
439 
442 
447 
449  InstSeqNum squashedSeqNum[Impl::MaxThreads];
450 
458 
460  bool addToDependents(DynInstPtr &new_inst);
461 
463  void addToProducers(DynInstPtr &new_inst);
464 
466  void addIfReady(DynInstPtr &inst);
467 
472  int countInsts();
473 
478  void dumpLists();
479 
483  void dumpInsts();
484 
489 
512  // Also include number of instructions rescheduled and replayed.
513 
517 // Stats::VectorDistribution queueResDist;
523 // Stats::VectorDistribution issueDelayDist;
524 
529 // Stats::Vector dist_unissued;
532 
535 
540  public:
547 
550 };
551 
552 #endif //__CPU_O3_INST_QUEUE_HH__
Stats::Scalar iqMiscInstsIssued
Stat for number of miscellaneous instructions issued.
Definition: inst_queue.hh:500
int wbOutstanding
Number of instructions currently in flight to FUs.
Definition: inst_queue.hh:441
void regStats()
Registers statistics.
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: inst_queue.hh:420
Stats::Scalar iqFloatInstsIssued
Stat for number of floating point instructions issued.
Definition: inst_queue.hh:494
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:269
Struct for comparing entries to be added to the priority queue.
Definition: inst_queue.hh:340
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Stats::Scalar fpAluAccesses
Definition: inst_queue.hh:549
void doSquash(ThreadID tid)
Does the actual squashing.
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute...
Stats::Scalar intAluAccesses
Definition: inst_queue.hh:548
void violation(DynInstPtr &store, DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Impl::CPUPol::IEW IEW
Definition: inst_queue.hh:89
Stats::Scalar iqInstsAdded
Stat for number of instructions added.
Definition: inst_queue.hh:486
InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
Constructs an IQ.
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
Definition: inst_queue.hh:384
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
Definition: inst_queue.hh:318
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
int wakeDependents(DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
void insertNonSpec(DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
InstSeqNum squashedSeqNum[Impl::MaxThreads]
The sequence number of the squashed instruction.
Definition: inst_queue.hh:449
Impl::DynInstPtr DynInstPtr
Definition: inst_queue.hh:87
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Stats::Scalar iqInstsIssued
Definition: inst_queue.hh:490
MemInterface * dcacheInterface
Cache interface.
Definition: inst_queue.hh:286
FU completion event class.
Definition: inst_queue.hh:98
Stats::Scalar iqMemInstsIssued
Stat for number of memory instructions issued.
Definition: inst_queue.hh:498
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
Definition: inst_queue.hh:341
A vector of scalar stats.
Definition: statistics.hh:2499
void insertBarrier(DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly...
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
unsigned numEntries
The number of entries in the instruction queue.
Definition: inst_queue.hh:432
std::list< DynInstPtr > instList[Impl::MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
Definition: inst_queue.hh:315
Declaration of Statistics objects.
virtual const char * description() const
Return a C string describing the event.
DynInstPtr inst
Executing instruction.
Definition: inst_queue.hh:101
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2475
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
std::vector< bool > regScoreboard
A cache of the recently woken registers.
Definition: inst_queue.hh:457
Stats::Scalar fpInstQueueWrites
Definition: inst_queue.hh:545
Impl::O3CPU O3CPU
Definition: inst_queue.hh:86
Impl::CPUPol::IssueStruct IssueStruct
Definition: inst_queue.hh:91
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
Definition: inst_queue.hh:326
void processFUCompletion(DynInstPtr &inst, int fu_idx)
Process FU completion event.
bool isFull()
Returns whether or not the IQ is full.
unsigned numFreeEntries()
Returns total number of free entries.
IQPolicy
IQ Resource Sharing Policy.
Definition: inst_queue.hh:407
int fuIdx
Index of the FU used for executing.
Definition: inst_queue.hh:104
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Stats::Scalar intInstQueueWakeupAccesses
Definition: inst_queue.hh:543
void blockMemInst(DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Stats::Scalar iqSquashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
Definition: inst_queue.hh:511
void addIfReady(DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:71
Array of linked list that maintains the dependencies between producing instructions and consuming ins...
Definition: dep_graph.hh:73
A simple distribution stat.
Definition: statistics.hh:2523
void completeMemInst(DynInstPtr &completed_inst)
Completes a memory operation.
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
Definition: inst_queue.hh:299
IEW * iewStage
Pointer to IEW stage.
Definition: inst_queue.hh:289
Stats::Scalar intInstQueueWrites
Definition: inst_queue.hh:542
void addToProducers(DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
Definition: inst_queue.hh:353
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread...
uint64_t InstSeqNum
Definition: inst_seq.hh:40
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit...
Definition: inst_queue.hh:362
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
Definition: inst_queue.hh:379
Stats::Scalar iqBranchInstsIssued
Stat for number of branch instructions issued.
Definition: inst_queue.hh:496
STL list class.
Definition: stl.hh:54
void addReadyMemInst(DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
unsigned count[Impl::MaxThreads]
Per Thread IQ count.
Definition: inst_queue.hh:423
void takeOverFrom()
Takes over execution from another CPU's thread.
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Definition: inst_queue.hh:302
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
Definition: inst_queue.hh:446
Stats::Scalar iqSquashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
Definition: inst_queue.hh:502
Stats::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
Definition: inst_queue.hh:539
std::string name() const
Returns the name of the IQ.
std::list< ListOrderEntry >::iterator ListOrderIt
Definition: inst_queue.hh:381
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
Definition: inst_queue.hh:331
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
Definition: inst_queue.hh:305
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2895
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
void resetState()
Resets all instruction queue state.
Memory dependency unit class.
Definition: mem_dep_unit.hh:81
~InstructionQueue()
Destructs the IQ.
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
void deferMemInst(DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk. ...
void squash(ThreadID tid)
Squashes instructions for a thread.
Stats::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
Definition: inst_queue.hh:531
DependencyGraph< DynInstPtr > dependGraph
Definition: inst_queue.hh:400
int countInsts()
Debugging function to count how many entries are in the IQ.
bool freeFU
Should the FU be added to the list to be freed upon completing this event.
Definition: inst_queue.hh:112
Stats::Scalar iqSquashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
Definition: inst_queue.hh:508
void resetEntries()
Resets max entries for all threads.
Stats::Scalar fpInstQueueReads
Definition: inst_queue.hh:544
static const OpClass Num_OpClasses
Definition: op_class.hh:92
std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, pqCompare > ReadyInstQueue
Definition: inst_queue.hh:348
Definition: eventq.hh:185
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
Definition: inst_queue.hh:364
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
void rescheduleMemInst(DynInstPtr &resched_inst)
Reschedules a memory instruction.
Stats::Scalar iqSquashedInstsExamined
Stat for number of squashed instructions examined when squashing.
Definition: inst_queue.hh:504
O3CPU * cpu
Pointer to the CPU.
Definition: inst_queue.hh:283
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Definition: inst_queue.hh:389
Stats::Scalar iqIntInstsIssued
Stat for number of integer instructions issued.
Definition: inst_queue.hh:492
Stats::Vector fuBusy
Number of times the FU was busy.
Definition: inst_queue.hh:537
void drainSanityCheck() const
Perform sanity checks after a drain.
Entry for the list age ordering by op class.
Definition: inst_queue.hh:367
std::list< DynInstPtr >::iterator ListIt
Definition: inst_queue.hh:95
unsigned maxEntries[Impl::MaxThreads]
Max IQ Entries Per Thread.
Definition: inst_queue.hh:426
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Stats::Scalar iqNonSpecInstsAdded
Stat for number of non-speculative instructions added.
Definition: inst_queue.hh:488
void printInsts()
Debug function to print all instructions.
Stats::Formula issueRate
Number of instructions issued per cycle.
Definition: inst_queue.hh:534
unsigned numPhysRegs
The number of physical registers in the CPU.
Definition: inst_queue.hh:438
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2515
Stats::Scalar fpInstQueueWakeupQccesses
Definition: inst_queue.hh:546
Stats::Scalar intInstQueueReads
Definition: inst_queue.hh:541
MemDepUnit memDepUnit[Impl::MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
Definition: inst_queue.hh:294
bool addToDependents(DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
void insert(DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
FUPool * fuPool
Function unit pool.
Definition: inst_queue.hh:308
FUCompletion(DynInstPtr &_inst, int fu_idx, InstructionQueue< Impl > *iq_ptr)
Construct a FU completion event.
bool isDrained() const
Determine if we are drained.
void recordProducer(DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ...
Definition: inst_queue.hh:208
IQPolicy iqPolicy
IQ sharing policy for SMT.
Definition: inst_queue.hh:414
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress)...
Definition: inst_queue.hh:323
InstructionQueue< Impl > * iqPtr
Pointer back to the instruction queue.
Definition: inst_queue.hh:107
A standard instruction queue class.
Definition: inst_queue.hh:82
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
Definition: inst_queue.hh:435
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
Stats::Distribution numIssuedDist
Distribution of number of instructions in the queue.
Definition: inst_queue.hh:519
unsigned freeEntries
Number of free IQ entries left.
Definition: inst_queue.hh:429
Stats::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
Definition: inst_queue.hh:528
void replayMemInst(DynInstPtr &replay_inst)
Replays a memory instruction.
Impl::CPUPol::MemDepUnit MemDepUnit
Definition: inst_queue.hh:90
Impl::CPUPol::TimeStruct TimeStruct
Definition: inst_queue.hh:92
ThreadID numThreads
Number of Total Threads.
Definition: inst_queue.hh:417

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