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miscregs.cc File Reference
#include "arch/arm/miscregs.hh"
#include <tuple>
#include "arch/arm/isa.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"

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Namespaces

 ArmISA
 

Functions

MiscRegIndex ArmISA::decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex ArmISA::decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex ArmISA::decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > ArmISA::canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr)
 
std::tuple< bool, bool > ArmISA::canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr)
 Check for permission to read coprocessor registers. More...
 
int ArmISA::flattenMiscRegNsBanked (MiscRegIndex reg, ThreadContext *tc)
 
int ArmISA::flattenMiscRegNsBanked (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
 ArmISA::preUnflattenMiscReg ()
 
int ArmISA::unflattenMiscReg (int reg)
 
bool ArmISA::canReadAArch64SysReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 
bool ArmISA::canWriteAArch64SysReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 
MiscRegIndex ArmISA::decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 

Variables

bitset< NUM_MISCREG_INFOS > ArmISA::miscRegInfo [NUM_MISCREGS]
 
int ArmISA::unflattenResultMiscReg [NUM_MISCREGS]
 If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
 

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