gem5
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
ns_gige.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Nathan Binkert
29  * Lisa Hsu
30  */
31 
37 #ifndef __DEV_NET_NS_GIGE_HH__
38 #define __DEV_NET_NS_GIGE_HH__
39 
40 #include "base/inet.hh"
41 #include "dev/io_device.hh"
42 #include "dev/net/etherdevice.hh"
43 #include "dev/net/etherint.hh"
44 #include "dev/net/etherpkt.hh"
45 #include "dev/net/ns_gige_reg.h"
46 #include "dev/net/pktfifo.hh"
47 #include "params/NSGigE.hh"
48 #include "sim/eventq.hh"
49 
50 // Hash filtering constants
51 const uint16_t FHASH_ADDR = 0x100;
52 const uint16_t FHASH_SIZE = 0x100;
53 
54 // EEPROM constants
55 const uint8_t EEPROM_READ = 0x2;
56 const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
57 const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
58 const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
59 const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
60 
64 struct dp_regs {
65  uint32_t command;
66  uint32_t config;
67  uint32_t mear;
68  uint32_t ptscr;
69  uint32_t isr;
70  uint32_t imr;
71  uint32_t ier;
72  uint32_t ihr;
73  uint32_t txdp;
74  uint32_t txdp_hi;
75  uint32_t txcfg;
76  uint32_t gpior;
77  uint32_t rxdp;
78  uint32_t rxdp_hi;
79  uint32_t rxcfg;
80  uint32_t pqcr;
81  uint32_t wcsr;
82  uint32_t pcr;
83  uint32_t rfcr;
84  uint32_t rfdr;
85  uint32_t brar;
86  uint32_t brdr;
87  uint32_t srr;
88  uint32_t mibc;
89  uint32_t vrcr;
90  uint32_t vtcr;
91  uint32_t vdr;
92  uint32_t ccsr;
93  uint32_t tbicr;
94  uint32_t tbisr;
95  uint32_t tanar;
96  uint32_t tanlpar;
97  uint32_t taner;
98  uint32_t tesr;
99 };
100 
101 struct dp_rom {
106  uint8_t perfectMatch[ETH_ADDR_LEN];
107 
113 };
114 
115 class NSGigEInt;
116 class Packet;
117 
121 class NSGigE : public EtherDevBase
122 {
123  public:
125  enum TxState
126  {
134  };
135 
137  enum RxState
138  {
146  };
147 
148  enum DmaState
149  {
155  };
156 
159  {
164  };
165 
166  protected:
170 
172  bool ioEnable;
173 #if 0
174  bool memEnable;
175  bool bmEnable;
176 #endif
177 
178  /*** BASIC STRUCTURES FOR TX/RX ***/
179  /* Data FIFOs */
182 
186  uint8_t *txPacketBufPtr;
187  uint8_t *rxPacketBufPtr;
188  uint32_t txXferLen;
189  uint32_t rxXferLen;
190  bool rxDmaFree;
191  bool txDmaFree;
192 
198 
199  /* tx State Machine */
201  bool txEnable;
202 
204  bool CTDD;
206  bool txHalt;
210  uint32_t txDescCnt;
212 
215  bool rxEnable;
216 
218  bool CRDD;
220  uint32_t rxPktBytes;
222  bool rxHalt;
226  uint32_t rxDescCnt;
228 
230 
233  bool eepromClk;
234  uint8_t eepromBitsToRx;
235  uint8_t eepromOpcode;
236  uint8_t eepromAddress;
237  uint16_t eepromData;
238 
239  protected:
242 
245 
246  void *rxDmaData;
248  int rxDmaLen;
249  bool doRxDmaRead();
250  bool doRxDmaWrite();
251 
252  void *txDmaData;
254  int txDmaLen;
255  bool doTxDmaRead();
256  bool doTxDmaWrite();
257 
258  void rxDmaReadDone();
261 
262  void rxDmaWriteDone();
265 
266  void txDmaReadDone();
269 
270  void txDmaWriteDone();
273 
276 
277  protected:
280 
281  void txReset();
282  void rxReset();
283  void regsReset();
284 
285  void rxKick();
288  friend void RxKickEvent::process();
290 
291  void txKick();
294  friend void TxKickEvent::process();
296 
297  void eepromKick();
298 
302  void transmit();
304  {
305  transmit();
306  if (txState == txFifoBlock)
307  txKick();
308  }
310  friend void TxEvent::process();
312 
313  void txDump() const;
314  void rxDump() const;
315 
320  bool rxFilter(const EthPacketPtr &packet);
325  bool acceptArp;
327 
331  void devIntrPost(uint32_t interrupts);
332  void devIntrClear(uint32_t interrupts);
333  void devIntrChangeMask();
334 
338  void cpuIntrPost(Tick when);
339  void cpuInterrupt();
340  void cpuIntrClear();
341 
343  friend void IntrEvent::process();
346 
347  public:
348  typedef NSGigEParams Params;
349  const Params *params() const {
350  return dynamic_cast<const Params *>(_params);
351  }
352 
353  NSGigE(Params *params);
354  ~NSGigE();
355 
356  EtherInt *getEthPort(const std::string &if_name, int idx) override;
357 
358  Tick writeConfig(PacketPtr pkt) override;
359 
360  Tick read(PacketPtr pkt) override;
361  Tick write(PacketPtr pkt) override;
362 
363  bool cpuIntrPending() const;
364  void cpuIntrAck() { cpuIntrClear(); }
365 
366  bool recvPacket(EthPacketPtr packet);
367  void transferDone();
368 
369  void serialize(CheckpointOut &cp) const override;
370  void unserialize(CheckpointIn &cp) override;
371 
372  void drainResume() override;
373 };
374 
375 /*
376  * Ethernet Interface for an Ethernet Device
377  */
378 class NSGigEInt : public EtherInt
379 {
380  private:
382 
383  public:
384  NSGigEInt(const std::string &name, NSGigE *d)
385  : EtherInt(name), dev(d)
386  { }
387 
388  virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
389  virtual void sendDone() { dev->transferDone(); }
390 };
391 
392 #endif // __DEV_NET_NS_GIGE_HH__
void txDmaWriteDone()
Definition: ns_gige.cc:1557
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: ns_gige.cc:2298
Tick txDelay
Definition: ns_gige.hh:278
bool cpuPendingIntr
Definition: ns_gige.hh:337
EventWrapper< NSGigE,&NSGigE::cpuInterrupt > IntrEvent
Definition: ns_gige.hh:342
TxEvent txEvent
Definition: ns_gige.hh:311
NSGigE(Params *params)
Definition: ns_gige.cc:99
Addr rxDmaAddr
Definition: ns_gige.hh:247
const uint8_t EEPROM_READ
Definition: ns_gige.hh:55
bool rxEnable
Definition: ns_gige.hh:215
EventWrapper< NSGigE,&NSGigE::txKick > TxKickEvent
Definition: ns_gige.hh:293
Addr rxFragPtr
ptr to the next byte in current fragment
Definition: ns_gige.hh:224
uint32_t mibc
Definition: ns_gige.hh:88
bool eepromClk
Definition: ns_gige.hh:233
void cpuIntrPost(Tick when)
Definition: ns_gige.cc:933
void rxDmaWriteDone()
Definition: ns_gige.cc:1110
Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy.
Definition: etherdevice.hh:134
uint8_t * txPacketBufPtr
Definition: ns_gige.hh:186
Tick intrDelay
Definition: ns_gige.hh:335
DmaState txDmaState
Definition: ns_gige.hh:211
dp_regs regs
device register file
Definition: ns_gige.hh:168
uint32_t tbisr
Definition: ns_gige.hh:94
EEPROMState
EEPROM State Machine States.
Definition: ns_gige.hh:158
bool cpuIntrPending() const
Definition: ns_gige.cc:1009
TxState txState
Definition: ns_gige.hh:200
void rxDmaReadDone()
Definition: ns_gige.cc:1080
const uint8_t EEPROM_PMATCH2_ADDR
Definition: ns_gige.hh:57
bool acceptBroadcast
Definition: ns_gige.hh:321
void cpuInterrupt()
Definition: ns_gige.cc:967
uint32_t tesr
Definition: ns_gige.hh:98
EventWrapper< NSGigE,&NSGigE::txDmaReadDone > txDmaReadEvent
Definition: ns_gige.hh:268
uint32_t command
Definition: ns_gige.hh:65
TxState
Transmit State Machine states.
Definition: ns_gige.hh:125
PacketFifo txFifo
Definition: ns_gige.hh:180
IntrEvent * intrEvent
Definition: ns_gige.hh:344
bool acceptPerfect
Definition: ns_gige.hh:324
TxKickEvent txKickEvent
Definition: ns_gige.hh:295
EEPROMState eepromState
EEPROM State Machine.
Definition: ns_gige.hh:232
NSGigEInt * interface
Definition: ns_gige.hh:345
uint32_t ptscr
Definition: ns_gige.hh:68
ns_desc64 rxDesc64
Definition: ns_gige.hh:197
const uint16_t FHASH_SIZE
Definition: ns_gige.hh:52
bool doTxDmaRead()
Definition: ns_gige.cc:1513
ns_desc64 txDesc64
Definition: ns_gige.hh:196
bool txHalt
halt the tx state machine after next packet
Definition: ns_gige.hh:206
uint32_t rxDescCnt
count of bytes remaining in the current descriptor
Definition: ns_gige.hh:226
uint32_t rxdp
Definition: ns_gige.hh:77
NSGigEInt(const std::string &name, NSGigE *d)
Definition: ns_gige.hh:384
Tick dmaReadFactor
Definition: ns_gige.hh:243
DmaState rxDmaState
Definition: ns_gige.hh:227
bool extstsEnable
Definition: ns_gige.hh:229
bool rxDmaFree
Definition: ns_gige.hh:190
uint8_t eepromAddress
Definition: ns_gige.hh:236
Tick intrTick
Definition: ns_gige.hh:336
uint32_t wcsr
Definition: ns_gige.hh:81
bool dmaDescFree
Definition: ns_gige.hh:274
void txKick()
Definition: ns_gige.cc:1574
void transferDone()
Definition: ns_gige.cc:2003
uint8_t eepromBitsToRx
Definition: ns_gige.hh:234
dp_rom rom
Definition: ns_gige.hh:169
Addr txFragPtr
ptr to the next byte in the current fragment
Definition: ns_gige.hh:208
uint32_t ccsr
Definition: ns_gige.hh:92
uint32_t brdr
Definition: ns_gige.hh:86
int txDmaLen
Definition: ns_gige.hh:254
ns_desc32 txDesc32
DescCaches.
Definition: ns_gige.hh:194
void regsReset()
Definition: ns_gige.cc:1043
uint32_t txdp
Definition: ns_gige.hh:73
EthPacketPtr rxPacket
Definition: ns_gige.hh:185
Tick rxDelay
Definition: ns_gige.hh:279
const uint8_t EEPROM_PMATCH0_ADDR
Definition: ns_gige.hh:59
DmaState
Definition: ns_gige.hh:148
bool acceptUnicast
Definition: ns_gige.hh:323
EventWrapper< NSGigE,&NSGigE::rxKick > RxKickEvent
Definition: ns_gige.hh:287
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:397
PacketFifo rxFifo
Definition: ns_gige.hh:181
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ns_gige.cc:408
uint32_t ihr
Definition: ns_gige.hh:72
uint32_t txcfg
Definition: ns_gige.hh:75
DmaDeviceParams Params
Definition: dma_device.hh:160
uint64_t Tick
Tick count type.
Definition: types.hh:63
void * rxDmaData
Definition: ns_gige.hh:246
void devIntrChangeMask()
Definition: ns_gige.cc:921
const uint8_t EEPROM_SIZE
Definition: ns_gige.hh:56
void rxKick()
Definition: ns_gige.cc:1127
bool doTxDmaWrite()
Definition: ns_gige.cc:1544
uint32_t rxdp_hi
Definition: ns_gige.hh:78
const Params * params() const
Definition: ns_gige.hh:349
void txDmaReadDone()
Definition: ns_gige.cc:1527
void drainResume() override
Resume execution after a successful drain.
Definition: ns_gige.cc:2109
const uint8_t EEPROM_PMATCH1_ADDR
Definition: ns_gige.hh:58
uint32_t gpior
Definition: ns_gige.hh:76
Bitfield< 9 > d
Definition: miscregs.hh:1375
Tick rxKickTick
Definition: ns_gige.hh:286
uint32_t rfdr
Definition: ns_gige.hh:84
uint32_t tanlpar
Definition: ns_gige.hh:96
Addr txDmaAddr
Definition: ns_gige.hh:253
uint32_t rfcr
Definition: ns_gige.hh:83
bool dmaDataFree
Definition: ns_gige.hh:275
bool CTDD
Current Transmit Descriptor Done.
Definition: ns_gige.hh:204
bool acceptMulticast
Definition: ns_gige.hh:322
EventWrapper< NSGigE,&NSGigE::txDmaWriteDone > txDmaWriteEvent
Definition: ns_gige.hh:272
NSGigE * dev
Definition: ns_gige.hh:381
bool acceptArp
Definition: ns_gige.hh:325
~NSGigE()
Definition: ns_gige.cc:138
NSGigEParams Params
Definition: ns_gige.hh:348
std::shared_ptr< EthPacketData > EthPacketPtr
Definition: etherpkt.hh:90
uint32_t config
Definition: ns_gige.hh:66
bool multicastHashEnable
Definition: ns_gige.hh:326
uint32_t pqcr
Definition: ns_gige.hh:80
void txReset()
Definition: ns_gige.cc:1013
uint32_t srr
Definition: ns_gige.hh:87
void * txDmaData
Definition: ns_gige.hh:252
void transmit()
Retransmit event.
Definition: ns_gige.cc:1462
Ethernet device registers.
Definition: ns_gige.hh:64
bool ioEnable
pci settings
Definition: ns_gige.hh:172
int rxDmaLen
Definition: ns_gige.hh:248
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
EtherInt * getEthPort(const std::string &if_name, int idx) override
Additional function to return the Port of a memory object.
Definition: ns_gige.cc:171
const uint16_t FHASH_ADDR
Definition: ns_gige.hh:51
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
bool rxFilter(const EthPacketPtr &packet)
Definition: ns_gige.cc:2016
Base Ethernet Device declaration.
void txDump() const
RxState
Receive State Machine States.
Definition: ns_gige.hh:137
Ethernet device register definitions for the National Semiconductor DP83820 Ethernet controller...
bool rxHalt
halt the rx state machine after current packet
Definition: ns_gige.hh:222
uint32_t vrcr
Definition: ns_gige.hh:89
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: ns_gige.cc:2125
EthPacketPtr txPacket
various helper vars
Definition: ns_gige.hh:184
uint8_t filterHash[FHASH_SIZE]
for hash table memory.
Definition: ns_gige.hh:112
ns_desc32 rxDesc32
Definition: ns_gige.hh:195
uint32_t vdr
Definition: ns_gige.hh:91
uint32_t rxcfg
Definition: ns_gige.hh:79
Tick writeConfig(PacketPtr pkt) override
This is to write to the PCI general configuration registers.
Definition: ns_gige.cc:147
EventWrapper< NSGigE,&NSGigE::rxDmaReadDone > rxDmaReadEvent
Definition: ns_gige.hh:260
Tick read(PacketPtr pkt) override
This reads the device registers, which are detailed in the NS83820 spec sheet.
Definition: ns_gige.cc:186
uint32_t vtcr
Definition: ns_gige.hh:90
std::ostream CheckpointOut
Definition: serialize.hh:67
void cpuIntrClear()
Definition: ns_gige.cc:990
uint32_t brar
Definition: ns_gige.hh:85
EventWrapper< NSGigE,&NSGigE::txEventTransmit > TxEvent
Definition: ns_gige.hh:309
uint16_t eepromData
Definition: ns_gige.hh:237
bool doRxDmaWrite()
Definition: ns_gige.cc:1097
RxKickEvent rxKickEvent
Definition: ns_gige.hh:289
uint32_t tbicr
Definition: ns_gige.hh:93
bool txEnable
Definition: ns_gige.hh:201
void rxDump() const
uint32_t txXferLen
Definition: ns_gige.hh:188
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:107
void cpuIntrAck()
Definition: ns_gige.hh:364
uint8_t perfectMatch[ETH_ADDR_LEN]
for perfect match memory.
Definition: ns_gige.hh:106
uint32_t txDescCnt
count of bytes remaining in the current descriptor
Definition: ns_gige.hh:210
Tick dmaWriteDelay
Definition: ns_gige.hh:241
const std::string & name() const
Return port name (for DPRINTF).
Definition: etherint.hh:60
uint8_t eepromOpcode
Definition: ns_gige.hh:235
EventWrapper< NSGigE,&NSGigE::rxDmaWriteDone > rxDmaWriteEvent
Definition: ns_gige.hh:264
uint32_t tanar
Definition: ns_gige.hh:95
void devIntrPost(uint32_t interrupts)
Interrupt management.
Definition: ns_gige.cc:822
uint32_t isr
Definition: ns_gige.hh:69
uint32_t pcr
Definition: ns_gige.hh:82
void rxReset()
Definition: ns_gige.cc:1028
bool rxFilterEnable
receive address filter
Definition: ns_gige.hh:319
RxState rxState
rx State Machine
Definition: ns_gige.hh:214
NS DP83820 Ethernet device model.
Definition: ns_gige.hh:121
uint32_t imr
Definition: ns_gige.hh:70
bool doRxDmaRead()
Definition: ns_gige.cc:1066
Tick dmaReadDelay
Definition: ns_gige.hh:240
bool CRDD
Current Receive Descriptor Done.
Definition: ns_gige.hh:218
bool txDmaFree
Definition: ns_gige.hh:191
void devIntrClear(uint32_t interrupts)
Definition: ns_gige.cc:879
uint8_t * rxPacketBufPtr
Definition: ns_gige.hh:187
void txEventTransmit()
Definition: ns_gige.hh:303
uint32_t taner
Definition: ns_gige.hh:97
uint32_t txdp_hi
Definition: ns_gige.hh:74
void eepromKick()
Advance the EEPROM state machine Called on rising edge of EEPROM clock bit in MEAR.
Definition: ns_gige.cc:1906
virtual bool recvPacket(EthPacketPtr pkt)
Definition: ns_gige.hh:388
uint32_t mear
Definition: ns_gige.hh:67
uint32_t ier
Definition: ns_gige.hh:71
uint32_t rxPktBytes
num of bytes in the current packet being drained from rxDataFifo
Definition: ns_gige.hh:220
uint32_t rxXferLen
Definition: ns_gige.hh:189
virtual void sendDone()
Definition: ns_gige.hh:389
Tick txKickTick
Definition: ns_gige.hh:292
Tick dmaWriteFactor
Definition: ns_gige.hh:244
bool recvPacket(EthPacketPtr packet)
Definition: ns_gige.cc:2059

Generated on Fri Jun 9 2017 13:03:46 for gem5 by doxygen 1.8.6