rename.hh

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/*
 * Copyright (c) 2012 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Kevin Lim
 */

#ifndef __CPU_O3_RENAME_HH__
#define __CPU_O3_RENAME_HH__

#include <list>
#include <utility>

#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/timebuf.hh"
#include "sim/probe/probe.hh"

struct DerivO3CPUParams;

template<class Impl>
class DefaultRename
{
  public:
    // Typedefs from the Impl.
    typedef typename Impl::CPUPol CPUPol;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::O3CPU O3CPU;

    // Typedefs from the CPUPol
    typedef typename CPUPol::DecodeStruct DecodeStruct;
    typedef typename CPUPol::RenameStruct RenameStruct;
    typedef typename CPUPol::TimeStruct TimeStruct;
    typedef typename CPUPol::FreeList FreeList;
    typedef typename CPUPol::RenameMap RenameMap;
    // These are used only for initialization.
    typedef typename CPUPol::IEW IEW;
    typedef typename CPUPol::Commit Commit;

    // Typedefs from the ISA.
    typedef TheISA::RegIndex RegIndex;

    // A deque is used to queue the instructions. Barrier insts must
    // be added to the front of the queue, which is the only reason for
    // using a deque instead of a queue. (Most other stages use a
    // queue)
    typedef std::deque<DynInstPtr> InstQueue;

  public:
    enum RenameStatus {
        Active,
        Inactive
    };

    enum ThreadStatus {
        Running,
        Idle,
        StartSquash,
        Squashing,
        Blocked,
        Unblocking,
        SerializeStall
    };

  private:
    RenameStatus _status;

    ThreadStatus renameStatus[Impl::MaxThreads];

    typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair;
    ProbePointArg<DynInstPtr> *ppRename;
    ProbePointArg<SeqNumRegPair> *ppSquashInRename;

  public:
    DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);

    std::string name() const;

    void regStats();

    void regProbePoints();

    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);

    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);

    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);

    void setIEWStage(IEW *iew_stage)
    { iew_ptr = iew_stage; }

    void setCommitStage(Commit *commit_stage)
    { commit_ptr = commit_stage; }

  private:
    IEW *iew_ptr;

    Commit *commit_ptr;

  public:
    void startupStage();

    void setActiveThreads(std::list<ThreadID> *at_ptr);

    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);

    void setFreeList(FreeList *fl_ptr);

    void setScoreboard(Scoreboard *_scoreboard);

    void drainSanityCheck() const;

    bool isDrained() const;

    void takeOverFrom();

    void squash(const InstSeqNum &squash_seq_num, ThreadID tid);

    void tick();

    void dumpHistory();

  private:
    void resetStage();

    void rename(bool &status_change, ThreadID tid);

    void renameInsts(ThreadID tid);

    void skidInsert(ThreadID tid);

    void sortInsts();

    bool skidsEmpty();

    void updateStatus();

    bool block(ThreadID tid);

    bool unblock(ThreadID tid);

    void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);

    void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);

    inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);

    inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);

    inline int calcFreeROBEntries(ThreadID tid);

    inline int calcFreeIQEntries(ThreadID tid);

    inline int calcFreeLQEntries(ThreadID tid);

    inline int calcFreeSQEntries(ThreadID tid);

    unsigned validInsts();

    void readStallSignals(ThreadID tid);

    bool checkStall(ThreadID tid);

    void readFreeEntries(ThreadID tid);

    bool checkSignalsAndUpdate(ThreadID tid);

    void serializeAfter(InstQueue &inst_list, ThreadID tid);

    struct RenameHistory {
        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
            : instSeqNum(_instSeqNum), archReg(_archReg),
              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
        {
        }

        InstSeqNum instSeqNum;
        RegIndex archReg;
        PhysRegIndex newPhysReg;
        PhysRegIndex prevPhysReg;
    };

    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];

    O3CPU *cpu;

    TimeBuffer<TimeStruct> *timeBuffer;

    typename TimeBuffer<TimeStruct>::wire fromIEW;

    typename TimeBuffer<TimeStruct>::wire fromCommit;

    typename TimeBuffer<TimeStruct>::wire toDecode;

    TimeBuffer<RenameStruct> *renameQueue;

    typename TimeBuffer<RenameStruct>::wire toIEW;

    TimeBuffer<DecodeStruct> *decodeQueue;

    typename TimeBuffer<DecodeStruct>::wire fromDecode;

    InstQueue insts[Impl::MaxThreads];

    InstQueue skidBuffer[Impl::MaxThreads];

    RenameMap *renameMap[Impl::MaxThreads];

    FreeList *freeList;

    std::list<ThreadID> *activeThreads;

    Scoreboard *scoreboard;

    int instsInProgress[Impl::MaxThreads];

    int loadsInProgress[Impl::MaxThreads];

    int storesInProgress[Impl::MaxThreads];

    bool wroteToTimeBuffer;

    struct FreeEntries {
        unsigned iqEntries;
        unsigned robEntries;
        unsigned lqEntries;
        unsigned sqEntries;
    };

    FreeEntries freeEntries[Impl::MaxThreads];

    bool emptyROB[Impl::MaxThreads];

    struct Stalls {
        bool iew;
        bool commit;
    };

    Stalls stalls[Impl::MaxThreads];

    DynInstPtr serializeInst[Impl::MaxThreads];

    bool serializeOnNextInst[Impl::MaxThreads];

    int iewToRenameDelay;

    int decodeToRenameDelay;

    unsigned commitToRenameDelay;

    unsigned renameWidth;

    unsigned commitWidth;

    unsigned toIEWIndex;

    bool blockThisCycle;

    bool resumeSerialize;

    bool resumeUnblocking;

    ThreadID numThreads;

    unsigned skidBufferMax;

    PhysRegIndex maxPhysicalRegs;

    enum FullSource {
        ROB,
        IQ,
        LQ,
        SQ,
        NONE
    };

    inline void incrFullStat(const FullSource &source);

    Stats::Scalar renameSquashCycles;
    Stats::Scalar renameIdleCycles;
    Stats::Scalar renameBlockCycles;
    Stats::Scalar renameSerializeStallCycles;
    Stats::Scalar renameRunCycles;
    Stats::Scalar renameUnblockCycles;
    Stats::Scalar renameRenamedInsts;
    Stats::Scalar renameSquashedInsts;
    Stats::Scalar renameROBFullEvents;
    Stats::Scalar renameIQFullEvents;
    Stats::Scalar renameLQFullEvents;
    Stats::Scalar renameSQFullEvents;
    Stats::Scalar renameFullRegistersEvents;
    Stats::Scalar renameRenamedOperands;
    Stats::Scalar renameRenameLookups;
    Stats::Scalar intRenameLookups;
    Stats::Scalar fpRenameLookups;
    Stats::Scalar renameCommittedMaps;
    Stats::Scalar renameUndoneMaps;
    Stats::Scalar renamedSerializing;
    Stats::Scalar renamedTempSerializing;
    Stats::Scalar renameSkidInsts;
};

#endif // __CPU_O3_RENAME_HH__