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pra_constants.hh
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1 /*
2  * Copyright (c) 2007 MIPS Technologies, Inc.
3  * All rights reserved.
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6  * modification, are permitted provided that the following conditions are
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10  * notice, this list of conditions and the following disclaimer in the
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14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Jaidev Patwardhan
29  */
30 
31 #ifndef __ARCH_RISCV_PRA_CONSTANTS_HH__
32 #define __ARCH_RISCV_PRA_CONSTANTS_HH__
33 
34 #include "arch/riscv/types.hh"
35 #include "base/bitunion.hh"
36 
37 namespace RiscvISA
38 {
39 
40 BitUnion32(IndexReg)
41  Bitfield<31> p;
42  // Need to figure out how to put in the TLB specific bits here
43  // For now, we assume that the entire length is used by the index
44  // field In reality, Index_HI = N-1, where
45  // N = Ceiling(log2(TLB Entries))
46  Bitfield<30, 0> index;
47 EndBitUnion(IndexReg)
48 
49 BitUnion32(RandomReg)
50  // This has a problem similar to the IndexReg index field. We'll keep
51  // both consistent at 30 for now
52  Bitfield<30, 0> random;
53 EndBitUnion(RandomReg)
54 
55 BitUnion64(EntryLoReg)
56  Bitfield<63, 30> fill;
57  Bitfield<29, 6> pfn; // Page frame number
58  Bitfield<5, 3> c; // Coherency attribute
59  Bitfield<2> d; // Dirty Bit
60  Bitfield<1> v; // Valid Bit
61  Bitfield<0> g; // Global Bit
62 EndBitUnion(EntryLoReg)
63 
64 BitUnion64(ContextReg)
65  Bitfield<63, 23> pteBase;
66  Bitfield<22, 4> badVPN2;
67  // Bits 3-0 are 0
68 EndBitUnion(ContextReg)
69 
70 BitUnion32(PageMaskReg)
71  // Bits 31-29 are 0
72  Bitfield<28, 13> mask;
73  Bitfield<12, 11> maskx;
74  // Bits 10-0 are zero
75 EndBitUnion(PageMaskReg)
76 
77 BitUnion32(PageGrainReg)
78  Bitfield<31, 30> aseUp;
79  Bitfield<29> elpa;
80  Bitfield<28> esp;
81  // Bits 27-13 are zeros
82  Bitfield<12, 8> aseDn;
83  // Bits 7-0 are zeros
84 EndBitUnion(PageGrainReg)
85 
86 BitUnion32(WiredReg)
87  // See note on Index register above
88  Bitfield<30, 0> wired;
89 EndBitUnion(WiredReg)
90 
91 BitUnion32(HWREnaReg)
92  Bitfield<31, 30> impl;
93  Bitfield<3, 0> mask;
94 EndBitUnion(HWREnaReg)
95 
96 BitUnion64(EntryHiReg)
97  Bitfield<63, 62> r;
98  Bitfield<61, 40> fill;
99  Bitfield<39, 13> vpn2;
100  Bitfield<12, 11> vpn2x;
101  Bitfield<7, 0> asid;
102 EndBitUnion(EntryHiReg)
103 
104 BitUnion32(StatusReg)
105  SubBitUnion(cu, 31, 28)
106  Bitfield<31> cu3;
107  Bitfield<30> cu2;
108  Bitfield<29> cu1;
109  Bitfield<28> cu0;
110  EndSubBitUnion(cu)
111  Bitfield<27> rp;
112  Bitfield<26> fr;
113  Bitfield<25> re;
114  Bitfield<24> mx;
115  Bitfield<23> px;
116  Bitfield<22> bev;
117  Bitfield<21> ts;
118  Bitfield<20> sr;
119  Bitfield<19> nmi;
120  // Bit 18 is zero
121  Bitfield<17, 16> impl;
122  Bitfield<15, 10> ipl;
123  SubBitUnion(im, 15, 8)
124  Bitfield<15> im7;
125  Bitfield<14> im6;
126  Bitfield<13> im5;
127  Bitfield<12> im4;
128  Bitfield<11> im3;
129  Bitfield<10> im2;
130  Bitfield<9> im1;
131  Bitfield<8> im0;
132  EndSubBitUnion(im)
133  Bitfield<7> kx;
134  Bitfield<6> sx;
135  Bitfield<5> ux;
136  Bitfield<4, 3> ksu;
137  Bitfield<4> um;
138  Bitfield<3> r0;
139  Bitfield<2> erl;
140  Bitfield<1> exl;
141  Bitfield<0> ie;
142 EndBitUnion(StatusReg)
143 
144 BitUnion32(IntCtlReg)
145  Bitfield<31, 29> ipti;
146  Bitfield<28, 26> ippci;
147  // Bits 26-10 are zeros
148  Bitfield<9, 5> vs;
149  // Bits 4-0 are zeros
150 EndBitUnion(IntCtlReg)
151 
152 BitUnion32(SRSCtlReg)
153  // Bits 31-30 are zeros
154  Bitfield<29, 26> hss;
155  // Bits 25-22 are zeros
156  Bitfield<21, 18> eicss;
157  // Bits 17-16 are zeros
158  Bitfield<15, 12> ess;
159  // Bits 11-10 are zeros
160  Bitfield<9, 6> pss;
161  // Bits 5-4 are zeros
162  Bitfield<3, 0> css;
163 EndBitUnion(SRSCtlReg)
164 
165 BitUnion32(SRSMapReg)
166  Bitfield<31, 28> ssv7;
167  Bitfield<27, 24> ssv6;
168  Bitfield<23, 20> ssv5;
169  Bitfield<19, 16> ssv4;
170  Bitfield<15, 12> ssv3;
171  Bitfield<11, 8> ssv2;
172  Bitfield<7, 4> ssv1;
173  Bitfield<3, 0> ssv0;
174 EndBitUnion(SRSMapReg)
175 
176 BitUnion32(CauseReg)
177  Bitfield<31> bd;
178  Bitfield<30> ti;
179  Bitfield<29, 28> ce;
180  Bitfield<27> dc;
181  Bitfield<26> pci;
182  // Bits 25-24 are zeros
183  Bitfield<23> iv;
184  Bitfield<22> wp;
185  // Bits 21-16 are zeros
186  Bitfield<15, 10> ripl;
187  SubBitUnion(ip, 15, 8)
188  Bitfield<15> ip7;
189  Bitfield<14> ip6;
190  Bitfield<13> ip5;
191  Bitfield<12> ip4;
192  Bitfield<11> ip3;
193  Bitfield<10> ip2;
194  Bitfield<9> ip1;
195  Bitfield<8> ip0;
196  EndSubBitUnion(ip);
197  // Bit 7 is zero
198  Bitfield<6, 2> excCode;
199  // Bits 1-0 are zeros
200 EndBitUnion(CauseReg)
201 
202 BitUnion32(PRIdReg)
203  Bitfield<31, 24> coOp;
204  Bitfield<23, 16> coId;
205  Bitfield<15, 8> procId;
206  Bitfield<7, 0> rev;
207 EndBitUnion(PRIdReg)
208 
209 BitUnion32(EBaseReg)
210  // Bit 31 is one
211  // Bit 30 is zero
212  Bitfield<29, 12> exceptionBase;
213  // Bits 11-10 are zeros
214  Bitfield<9, 9> cpuNum;
215 EndBitUnion(EBaseReg)
216 
217 BitUnion32(ConfigReg)
218  Bitfield<31> m;
219  Bitfield<30, 28> k23;
220  Bitfield<27, 25> ku;
221  Bitfield<24, 16> impl;
222  Bitfield<15> be;
223  Bitfield<14, 13> at;
224  Bitfield<12, 10> ar;
225  Bitfield<9, 7> mt;
226  // Bits 6-4 are zeros
227  Bitfield<3> vi;
228  Bitfield<2, 0> k0;
229 EndBitUnion(ConfigReg)
230 
231 BitUnion32(Config1Reg)
232  Bitfield<31> m;
233  Bitfield<30, 25> mmuSize;
234  Bitfield<24, 22> is;
235  Bitfield<21, 19> il;
236  Bitfield<18, 16> ia;
237  Bitfield<15, 13> ds;
238  Bitfield<12, 10> dl;
239  Bitfield<9, 7> da;
240  Bitfield<6> c2;
241  Bitfield<5> md;
242  Bitfield<4> pc;
243  Bitfield<3> wr;
244  Bitfield<2> ca;
245  Bitfield<1> ep;
246  Bitfield<0> fp;
247 EndBitUnion(Config1Reg)
248 
249 BitUnion32(Config2Reg)
250  Bitfield<31> m;
251  Bitfield<30, 28> tu;
252  Bitfield<27, 24> ts;
253  Bitfield<23, 20> tl;
254  Bitfield<19, 16> ta;
255  Bitfield<15, 12> su;
256  Bitfield<11, 8> ss;
257  Bitfield<7, 4> sl;
258  Bitfield<3, 0> sa;
259 EndBitUnion(Config2Reg)
260 
261 BitUnion32(Config3Reg)
262  Bitfield<31> m;
263  // Bits 30-11 are zeros
264  Bitfield<10> dspp;
265  // Bits 9-8 are zeros
266  Bitfield<7> lpa;
267  Bitfield<6> veic;
268  Bitfield<5> vint;
269  Bitfield<4> sp;
270  // Bit 3 is zero
271  Bitfield<2> mt;
272  Bitfield<1> sm;
273  Bitfield<0> tl;
274 EndBitUnion(Config3Reg)
275 
276 BitUnion64(WatchLoReg)
277  Bitfield<63, 3> vaddr;
278  Bitfield<2> i;
279  Bitfield<1> r;
280  Bitfield<0> w;
281 EndBitUnion(WatchLoReg)
282 
283 BitUnion32(WatchHiReg)
284  Bitfield<31> m;
285  Bitfield<30> g;
286  // Bits 29-24 are zeros
287  Bitfield<23, 16> asid;
288  // Bits 15-12 are zeros
289  Bitfield<11, 3> mask;
290  Bitfield<2> i;
291  Bitfield<1> r;
292  Bitfield<0> w;
293 EndBitUnion(WatchHiReg)
294 
295 BitUnion32(PerfCntCtlReg)
296  Bitfield<31> m;
297  Bitfield<30> w;
298  // Bits 29-11 are zeros
299  Bitfield<10, 5> event;
300  Bitfield<4> ie;
301  Bitfield<3> u;
302  Bitfield<2> s;
303  Bitfield<1> k;
304  Bitfield<0> exl;
305 EndBitUnion(PerfCntCtlReg)
306 
307 BitUnion32(CacheErrReg)
308  Bitfield<31> er;
309  Bitfield<30> ec;
310  Bitfield<29> ed;
311  Bitfield<28> et;
312  Bitfield<27> es;
313  Bitfield<26> ee;
314  Bitfield<25> eb;
315  Bitfield<24, 22> impl;
316  Bitfield<22, 0> index;
317 EndBitUnion(CacheErrReg)
318 
319 BitUnion32(TagLoReg)
320  Bitfield<31, 8> pTagLo;
321  Bitfield<7, 6> pState;
322  Bitfield<5> l;
323  Bitfield<4, 3> impl;
324  // Bits 2-1 are zeros
325  Bitfield<0> p;
326 EndBitUnion(TagLoReg)
327 
328 } // namespace RiscvISA
329 
330 #endif
Bitfield< 0 > ie
Bitfield< 19 > nmi
Bitfield< 10 > im2
Bitfield< 31 > cu3
Bitfield< 3, 0 > css
Bitfield< 3, 0 > sa
Bitfield< 27 > dc
Bitfield< 22, 4 > badVPN2
Bitfield< 18, 16 > ia
Bitfield< 23 > px
Bitfield< 6 > c2
Bitfield< 29 > cu1
Bitfield< 0 > m
Definition: miscregs.hh:1577
Bitfield< 6 > sx
Bitfield< 28 > cu0
Bitfield< 25 > eb
Bitfield< 21, 19 > il
Bitfield< 12, 11 > vpn2x
Bitfield< 10, 5 > event
Bitfield< 19, 16 > ssv4
Bitfield< 12, 10 > dl
Bitfield< 23 > iv
Bitfield< 7, 6 > pState
Bitfield< 26 > fr
Bitfield< 8 > ip0
Bitfield< 15, 10 > ripl
Bitfield< 4 > um
Bitfield< 14 > ip6
Bitfield< 5 > md
Bitfield< 15, 10 > ipl
Bitfield< 9, 6 > pss
Bitfield< 27 > es
Bitfield< 3 > wr
Bitfield< 9, 9 > cpuNum
Bitfield< 28 > esp
Bitfield< 23, 20 > tl
Bitfield< 26 > pci
Bitfield< 14, 13 > at
Bitfield< 23, 16 > coId
Bitfield< 2 > ca
Bitfield< 0 > p
Bitfield< 11 > im3
Bitfield< 30, 0 > index
Bitfield< 15, 13 > ds
Bitfield< 12, 8 > aseDn
Bitfield< 7, 0 > rev
Bitfield< 12, 10 > ar
Bitfield< 27, 25 > ku
Bitfield< 13 > im5
Bitfield< 26 > ee
Bitfield< 28, 26 > ippci
Bitfield< 30, 28 > k23
Bitfield< 11, 8 > ssv2
Bitfield< 30 > ec
BitUnion32(IndexReg) Bitfield< 31 > p
Bitfield< 4 > sp
Bitfield< 4 > pc
Bitfield< 7, 0 > asid
Bitfield< 9 > ip1
Bitfield< 1 > sm
Bitfield< 2 > d
Bitfield< 11 > ip3
Bitfield< 2 > erl
Bitfield< 27, 24 > ssv6
Bitfield< 0 > fp
Bitfield< 10 > dspp
Bitfield< 12 > ip4
Bitfield< 25 > re
Bitfield< 13 > ip5
Bitfield< 2 > i
Bitfield< 22 > wp
Bitfield< 15, 12 > ssv3
Bitfield< 29, 28 > ce
Bitfield< 24 > mx
Bitfield< 9 > im1
Bitfield< 24, 22 > is
Bitfield< 29 > elpa
Bitfield< 8 > im0
Bitfield< 9, 7 > mt
Bitfield< 15, 2 > bd
Definition: types.hh:63
Bitfield< 14 > im6
Bitfield< 3 > u
Bitfield< 1 > k
EndSubBitUnion(cu) Bitfield< 27 > rp
Bitfield< 29, 6 > pfn
Bitfield< 6, 2 > excCode
SubBitUnion(im, 15, 8) Bitfield< 15 > im7
Bitfield< 3 > vi
Bitfield< 6 > veic
Bitfield< 22 > bev
Bitfield< 0 > g
Bitfield< 5 > vint
Bitfield< 30 > ti
Bitfield< 15, 8 > procId
Bitfield< 20 > sr
Bitfield< 7, 4 > ssv1
Bitfield< 15, 12 > ess
Bitfield< 12, 11 > maskx
Bitfield< 9, 5 > vs
Bitfield< 1 > ep
Bitfield< 2, 0 > k0
Bitfield< 7 > lpa
Bitfield< 5 > l
Bitfield< 15, 12 > su
Bitfield< 28 > et
Bitfield< 30 > cu2
Bitfield< 4, 3 > ksu
Bitfield< 1 > v
Bitfield< 1 > exl
EndBitUnion(IndexReg) BitUnion32(RandomReg) Bitfield< 30
Bitfield< 21, 18 > eicss
Bitfield< 12 > im4
Bitfield< 9, 7 > da
Bitfield< 5 > ux
Bitfield< 7, 4 > sl
Bitfield< 30, 28 > tu
Bitfield< 3, 0 > ssv0
Bitfield< 3 > r0
bool ip(TxDesc *d)
Bitfield< 29 > ed
Bitfield< 15 > be
Bitfield< 5, 3 > c
#define BitUnion64(name)
Definition: bitunion.hh:327
Bitfield< 10 > ip2
Bitfield< 19, 16 > ta
Bitfield< 23, 20 > ssv5
Bitfield< 39, 13 > vpn2
Bitfield< 30, 25 > mmuSize
Bitfield< 21 > ts
Bitfield< 2 > s
Bitfield< 11, 8 > ss
Bitfield< 0 > w

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