serial_link.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2011-2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2006 The Regents of The University of Michigan
 * Copyright (c) 2015 The University of Bologna
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Ali Saidi
 *          Steve Reinhardt
 *          Andreas Hansson
 *          Erfan Azarkhish
 */

#ifndef __MEM_SERIAL_LINK_HH__
#define __MEM_SERIAL_LINK_HH__

#include <deque>

#include "base/types.hh"
#include "mem/mem_object.hh"
#include "params/SerialLink.hh"

class SerialLink : public MemObject
{
  protected:

    class DeferredPacket
    {

      public:

        const Tick tick;
        const PacketPtr pkt;

        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
    };

    // Forward declaration to allow the slave port to have a pointer
    class SerialLinkMasterPort;

    class SerialLinkSlavePort : public SlavePort
    {

      private:

        SerialLink& serial_link;

        SerialLinkMasterPort& masterPort;

        const Cycles delay;

        const AddrRangeList ranges;

        std::deque<DeferredPacket> transmitList;

        unsigned int outstandingResponses;

        bool retryReq;

        unsigned int respQueueLimit;

        bool respQueueFull() const;

        void trySendTiming();

        EventWrapper<SerialLinkSlavePort,
                     &SerialLinkSlavePort::trySendTiming> sendEvent;

      public:

        SerialLinkSlavePort(const std::string& _name, SerialLink&
                        _serial_link, SerialLinkMasterPort& _masterPort,
                        Cycles _delay, int _resp_limit, const
                        std::vector<AddrRange>& _ranges);

        void schedTimingResp(PacketPtr pkt, Tick when);

        void retryStalledReq();

      protected:

        bool recvTimingReq(PacketPtr pkt);

        void recvRespRetry();

        Tick recvAtomic(PacketPtr pkt);

        void recvFunctional(PacketPtr pkt);

        AddrRangeList getAddrRanges() const;
    };


    class SerialLinkMasterPort : public MasterPort
    {

      private:

        SerialLink& serial_link;

        SerialLinkSlavePort& slavePort;

        const Cycles delay;

        std::deque<DeferredPacket> transmitList;

        const unsigned int reqQueueLimit;

        void trySendTiming();

        EventWrapper<SerialLinkMasterPort,
                     &SerialLinkMasterPort::trySendTiming> sendEvent;

      public:

        SerialLinkMasterPort(const std::string& _name, SerialLink&
                         _serial_link, SerialLinkSlavePort& _slavePort, Cycles
                         _delay, int _req_limit);

        bool reqQueueFull() const;

        void schedTimingReq(PacketPtr pkt, Tick when);

        bool checkFunctional(PacketPtr pkt);

      protected:

        bool recvTimingResp(PacketPtr pkt);

        void recvReqRetry();
    };

    SerialLinkSlavePort slavePort;

    SerialLinkMasterPort masterPort;

    unsigned num_lanes;

    uint64_t link_speed;

  public:

    virtual BaseMasterPort& getMasterPort(const std::string& if_name,
                                          PortID idx = InvalidPortID);
    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
                                        PortID idx = InvalidPortID);

    virtual void init();

    typedef SerialLinkParams Params;

    SerialLink(SerialLinkParams *p);
};

#endif //__MEM_SERIAL_LINK_HH__