gem5
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
Public Attributes | List of all members
TimeBufStruct< Impl >::commitComm Struct Reference

#include <comm.hh>

Public Attributes

TheISA::PCState pc
 The pc of the next instruction to execute. More...
 
DynInstPtr mispredictInst
 Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured. More...
 
DynInstPtr squashInst
 Instruction that caused the a non-mispredict squash. More...
 
DynInstPtr strictlyOrderedLoad
 Hack for now to send back a strictly ordered access to the IEW stage. More...
 
InstSeqNum nonSpecSeqNum
 Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction. More...
 
InstSeqNum doneSeqNum
 Represents the instruction that has either been retired or squashed. More...
 
unsigned freeROBEntries
 Tell Rename how many free entries it has in the ROB. More...
 
bool squash
 
bool robSquashing
 
bool usedROB
 Rename should re-read number of free rob entries. More...
 
bool emptyROB
 Notify Rename that the ROB is empty. More...
 
bool branchTaken
 Was the branch taken or not. More...
 
bool interruptPending
 If an interrupt is pending and fetch should stall. More...
 
bool clearInterrupt
 If the interrupt ended up being cleared before being handled. More...
 
bool strictlyOrdered
 Hack for now to send back an strictly ordered access to the IEW stage. More...
 

Detailed Description

template<class Impl>
struct TimeBufStruct< Impl >::commitComm

Definition at line 163 of file comm.hh.

Member Data Documentation

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::branchTaken

Was the branch taken or not.

Definition at line 214 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::clearInterrupt

If the interrupt ended up being cleared before being handled.

Definition at line 218 of file comm.hh.

template<class Impl >
InstSeqNum TimeBufStruct< Impl >::commitComm::doneSeqNum

Represents the instruction that has either been retired or squashed.

Similar to having a single bus that broadcasts the retired or squashed sequence number.

Definition at line 199 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::emptyROB

Notify Rename that the ROB is empty.

Definition at line 211 of file comm.hh.

template<class Impl >
unsigned TimeBufStruct< Impl >::commitComm::freeROBEntries

Tell Rename how many free entries it has in the ROB.

Definition at line 202 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::interruptPending

If an interrupt is pending and fetch should stall.

Definition at line 216 of file comm.hh.

template<class Impl >
DynInstPtr TimeBufStruct< Impl >::commitComm::mispredictInst

Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.

Definition at line 183 of file comm.hh.

template<class Impl >
InstSeqNum TimeBufStruct< Impl >::commitComm::nonSpecSeqNum

Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.

Definition at line 194 of file comm.hh.

template<class Impl >
TheISA::PCState TimeBufStruct< Impl >::commitComm::pc

The pc of the next instruction to execute.

This is the next instruction for a branch mispredict, but the same instruction for order violation and the like

Definition at line 179 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::robSquashing

Definition at line 205 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::squash

Definition at line 204 of file comm.hh.

template<class Impl >
DynInstPtr TimeBufStruct< Impl >::commitComm::squashInst

Instruction that caused the a non-mispredict squash.

Definition at line 186 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::strictlyOrdered

Hack for now to send back an strictly ordered access to the IEW stage.

Definition at line 222 of file comm.hh.

template<class Impl >
DynInstPtr TimeBufStruct< Impl >::commitComm::strictlyOrderedLoad

Hack for now to send back a strictly ordered access to the IEW stage.

Definition at line 190 of file comm.hh.

template<class Impl >
bool TimeBufStruct< Impl >::commitComm::usedROB

Rename should re-read number of free rob entries.

Definition at line 208 of file comm.hh.


The documentation for this struct was generated from the following file:

Generated on Fri Jun 9 2017 13:04:21 for gem5 by doxygen 1.8.6