ufs_device.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2013-2015 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Rene de Jong
 */


#ifndef __DEV_ARM_UFS_DEVICE_HH__
#define __DEV_ARM_UFS_DEVICE_HH__

#include <deque>

#include "base/addr_range.hh"
#include "base/bitfield.hh"
#include "base/statistics.hh"
#include "debug/UFSHostDevice.hh"
#include "dev/arm/abstract_nvm.hh"
#include "dev/arm/base_gic.hh"
#include "dev/storage/disk_image.hh"
#include "dev/dma_device.hh"
#include "dev/io_device.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/UFSHostDevice.hh"
#include "sim/serialize.hh"
#include "sim/stats.hh"

class UFSHostDevice : public DmaDevice
{
  public:

    UFSHostDevice(const UFSHostDeviceParams* p);

    DrainState drain() override;
    void checkDrain();
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

  private:
    struct HCIMem {
        uint32_t HCCAP;
        uint32_t HCversion;
        uint32_t HCHCDDID;
        uint32_t HCHCPMID;

        uint32_t ORInterruptStatus;
        uint32_t ORInterruptEnable;
        uint32_t ORHostControllerStatus;
        uint32_t ORHostControllerEnable;
        uint32_t ORUECPA;
        uint32_t ORUECDL;
        uint32_t ORUECN;
        uint32_t ORUECT;
        uint32_t ORUECDME;
        uint32_t ORUTRIACR;

        uint32_t vendorSpecific;

        uint32_t TRUTRLBA;
        uint32_t TRUTRLBAU;
        uint32_t TRUTRLDBR;
        uint32_t TRUTRLCLR;
        uint32_t TRUTRLRSR;

        uint32_t TMUTMRLBA;
        uint32_t TMUTMRLBAU;
        uint32_t TMUTMRLDBR;
        uint32_t TMUTMRLCLR;
        uint32_t TMUTMRLRSR;

        uint32_t CMDUICCMDR;
        uint32_t CMDUCMDARG1;
        uint32_t CMDUCMDARG2;
        uint32_t CMDUCMDARG3;
    };

    struct UTPUPIUHeader {
        uint32_t dWord0;
        uint32_t dWord1;
        uint32_t dWord2;
    };

    struct UTPUPIURSP {
        struct UTPUPIUHeader header;
        uint32_t residualTransferCount;
        uint32_t reserved[4];
        uint16_t senseDataLen;
        uint8_t senseData[18];
    };

    struct UTPUPIUTaskReq {
        struct UTPUPIUHeader header;
        uint32_t inputParam1;
        uint32_t inputParam2;
        uint32_t inputParam3;
        uint32_t reserved[2];
    };

    struct UFSHCDSGEntry {
        uint32_t baseAddr;
        uint32_t upperAddr;
        uint32_t reserved;
        uint32_t size;
    };

    struct UTPTransferCMDDesc {
        uint8_t commandUPIU[128];
        uint8_t responseUPIU[128];
        struct UFSHCDSGEntry PRDTable[128];
    };

    struct UPIUMessage {
        struct UTPUPIUHeader header;
        uint32_t dataOffset;
        uint32_t dataCount;
        std::vector<uint32_t> dataMsg;
    };

    struct UTPTransferReqDesc {

        struct RequestDescHeader {
            uint32_t dWord0;
            uint32_t dWord1;
            uint32_t dWord2;
            uint32_t dWord3;
        } header;

        /* DW 4-5*/
        uint32_t commandDescBaseAddrLo;
        uint32_t commandDescBaseAddrHi;

        /* DW 6 */
        uint16_t responseUPIULength;
        uint16_t responseUPIUOffset;

        /* DW 7 */
        uint16_t PRDTableLength;
        uint16_t PRDTableOffset;
    };

    struct SCSIReply {
        uint8_t status;
        uint32_t msgSize;
        uint8_t LUN;
        struct UPIUMessage message;
        uint8_t senseSize;
        uint8_t expectMore;//0x01 is for writes, 0x02 is for reads
        uint64_t offset;
        uint8_t senseCode[19];
    };

    struct LUNInfo {
        uint32_t dWord0;
        uint32_t dWord1;
        uint32_t vendor0;
        uint32_t vendor1;
        uint32_t product0;
        uint32_t product1;
        uint32_t product2;
        uint32_t product3;
        uint32_t productRevision;
    };

    struct transferInfo {
        std::vector <uint8_t> buffer;
        uint32_t size;
        uint64_t offset;
        uint32_t filePointer;
        uint32_t lunID;
    };

    struct transferDoneInfo {
        Addr responseStartAddr;
        uint32_t reqPos;
        struct UTPUPIURSP requestOut;
        uint32_t size;
        Addr address;
        uint8_t *destination;
        bool finished;
        uint32_t lunID;
    };

    struct transferStart {
        struct UTPTransferReqDesc* destination;
        uint32_t mask;
        Addr address;
        uint32_t size;
        uint32_t done;
        uint32_t lun_id;
    };

    struct taskStart {
        struct UTPUPIUTaskReq destination;
        uint32_t mask;
        Addr address;
        uint32_t size;
        bool done;
    };

    struct SCSIResumeInfo {
        struct UTPTransferReqDesc* RequestIn;
        int reqPos;
        Addr finalAddress;
        uint32_t finalSize;
        std::vector <uint8_t> destination;
        uint32_t done;
    };

    struct writeToDiskBurst {
        Addr start;
        uint64_t SCSIDiskOffset;
        uint32_t size;
        uint32_t LUN;
    };

    struct UFSHostDeviceStats {
        Stats::Scalar currentSCSIQueue;
        Stats::Scalar currentReadSSDQueue;
        Stats::Scalar currentWriteSSDQueue;

        Stats::Scalar totalReadSSD;
        Stats::Scalar totalWrittenSSD;
        Stats::Scalar totalReadDiskTransactions;
        Stats::Scalar totalWriteDiskTransactions;
        Stats::Scalar totalReadUFSTransactions;
        Stats::Scalar totalWriteUFSTransactions;

        Stats::Formula averageReadSSDBW;
        Stats::Formula averageWriteSSDBW;

        Stats::Average averageSCSIQueue;
        Stats::Average averageReadSSDQueue;
        Stats::Average averageWriteSSDQueue;

        Stats::Formula curDoorbell;
        Stats::Scalar maxDoorbell;
        Stats::Average averageDoorbell;

        Stats::Histogram transactionLatency;
        Stats::Histogram idleTimes;
    };

    class UFSSCSIDevice: SimObject
    {
      public:
        UFSSCSIDevice(const UFSHostDeviceParams* p, uint32_t lun_id, Callback*
                      transfer_cb, Callback *read_cb);
        ~UFSSCSIDevice();

        struct SCSIReply SCSICMDHandle(uint32_t* SCSI_msg);

        void readFlash(uint8_t* readaddr, uint64_t offset, uint32_t size);

        void writeFlash(uint8_t* writeaddr, uint64_t offset, uint32_t size);

        bool finishedCommand() const {return transferCompleted;};

        void clearSignal() {transferCompleted = false;};

        bool finishedRead() const {return readCompleted;};

        void clearReadSignal() {readCompleted = false;};

        void SSDReadStart(uint32_t total_read);
        void SSDWriteStart();

        void setTotalWrite(uint32_t total_write) {totalWrite = total_write;};

        transferDoneInfo transferInfo;

        std::deque<struct SCSIResumeInfo> SCSIInfoQueue;

        std::deque<struct transferInfo> SSDReadInfo;

        std::deque<struct transferInfo> SSDWriteDoneInfo;

      private:
        void readCallback();

        void SSDReadDone();

        void SSDWriteDone();

        void statusCheck(uint8_t status, uint8_t* sensecodelist);

        void setSignal() {transferCompleted = true;};

        void setReadSignal() {readCompleted = true;};

        DiskImage* flashDisk;
        AbstractNVM* flashDevice;

        const uint32_t blkSize;
        const uint32_t lunAvail;
        const uint64_t diskSize;
        const uint32_t capacityLower;
        const uint32_t capacityUpper;

        struct LUNInfo lunInfo;
        const uint32_t lunID;

        bool transferCompleted;
        bool readCompleted;

        uint32_t totalRead;
        uint32_t totalWrite;

        uint32_t amountOfWriteTransfers;
        uint32_t amountOfReadTransfers;

        Callback* signalDone;
        Callback* deviceReadCallback;

        Callback* memReadCallback;
        Callback* memWriteCallback;

        /*
         * Default response header layout. For more information refer to
         * chapter 7 http://www.jedec.org/standards-documents/results/jesd220
         */
        static const unsigned int UPIUHeaderDataIndWord0 = 0x0000C022;
        static const unsigned int UPIUHeaderDataIndWord1 = 0x00000000;
        static const unsigned int UPIUHeaderDataIndWord2 = 0x40000000;

        /*
         * SCSI mode pages values assigned in ufs_device.cc
         * The mode pages give device specific information via the SCSI
         * protocol. They are defined in
         * http://www.jedec.org/standards-documents/results/jesd220
         */
        static const unsigned int controlPage[3];
        static const unsigned int recoveryPage[3];
        static const unsigned int cachingPage[5];

        /*
         * SCSI command set; defined in
         * http://www.jedec.org/standards-documents/results/jesd220
         */
        enum SCSICommandSet {
            SCSIInquiry = 0x12,
            SCSIRead6 = 0x08,
            SCSIRead10 = 0x28,
            SCSIRead16 = 0x88,
            SCSIReadCapacity10 = 0x25,
            SCSIReadCapacity16 = 0x9E,
            SCSIReportLUNs = 0xA0,
            SCSIStartStop = 0x1B,
            SCSITestUnitReady = 0x00,
            SCSIVerify10 = 0x2F,
            SCSIWrite6 = 0x0A,
            SCSIWrite10 = 0x2A,
            SCSIWrite16 = 0x8A,
            SCSIFormatUnit = 0x04,
            SCSISendDiagnostic = 0x1D,
            SCSISynchronizeCache = 0x35,
            //UFS SCSI additional command set for full functionality
            SCSIModeSelect10 = 0x55,
            SCSIModeSense6 = 0x1A,
            SCSIModeSense10 = 0x5A,
            SCSIRequestSense = 0x03,
            SCSIUnmap = 0x42,
            SCSIWriteBuffer = 0x3B,
            SCSIReadBuffer = 0x3C,
            //SCSI commands not supported by UFS; but Linux send them anyway
            SCSIMaintenanceIn = 0xA3
        };

        /*
         * SCSI status codes; defined in
         * http://www.jedec.org/standards-documents/results/jesd220
         */
        enum SCSIStatusCodes {
            SCSIGood = 0x00,
            SCSICheckCondition = 0x02,
            SCSIConditionGood = 0x04,
            SCSIBusy = 0x08,
            SCSIIntermediateGood = 0x10,
            SCSIIntermediatCGood = 0x14,
            SCSIReservationConflict = 0x18,
            SCSICommandTerminated = 0x22,
            SCSITaskSetFull = 0x28,
            SCSIACAActive = 0x30,
            SCSITaskAborted = 0x40
        };

        /*
         * SCSI sense codes; defined in
         * http://www.jedec.org/standards-documents/results/jesd220
         */
        enum SCSISenseCodes {
            SCSINoSense = 0x00,
            SCSIRecoverdError = 0x01,
            SCSINotReady = 0x02,
            SCSIMediumError = 0x03,
            SCSIHardwareError = 0x04,
            SCSIIllegalRequest = 0x05,
            SCSIUnitAttention = 0x06,
            SCSIDataProtect = 0x07,
            SCSIBlankCheck = 0x08,
            SCSIAbortedCommand = 0x0B,
            SCSIVolumeOverflow = 0x0D,
            SCSIMisCompare = 0x0E
        };

    };

    //All access functions are inherrited; no need to make them public
    AddrRangeList getAddrRanges() const override;

    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
    // end of access functions

    void setValues();

    void requestHandler();

    void commandHandler();

    void taskStart();

    void taskHandler(struct UTPUPIUTaskReq* request_in,
                     uint32_t req_pos, Addr finaladdress, uint32_t finalsize);

    void transferStart();

    void transferHandler(struct UTPTransferReqDesc*
                         request_in, int req_pos, Addr finaladdress,
                         uint32_t finalsize, uint32_t done);

    void SCSIStart();

    void SCSIResume(uint32_t lun_id);

    void LUNSignal();

    void transferDone(Addr responseStartAddr, uint32_t req_pos,
                      struct UTPUPIURSP request_out, uint32_t size,
                      Addr address, uint8_t* destination, bool finished,
                      uint32_t lun_id);
    void finalUTP();

    void clearInterrupt();
    void generateInterrupt();

    void writeDevice(Event* additional_action, bool toDisk, Addr start,
                     int size, uint8_t* destination, uint64_t SCSIDiskOffset,
                     uint32_t lun_id);
    void readDevice(bool lastTransfer, Addr SCSIStart, uint32_t SCSISize,
                    uint8_t* SCSIDestination, bool no_cache,
                    Event* additional_action);

    void manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t
                             sg_table_length, struct UFSHCDSGEntry* sglist);
    void manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t offset,
                            uint32_t sg_table_length,
                            struct UFSHCDSGEntry* sglist);

    void readDone();

    void writeDone();

    void readCallback();

    void readGarbage();

    void regStats() override;

    const Addr pioAddr;
    const Addr pioSize;
    const Tick pioDelay;
    const int intNum;
    BaseGic* gic;
    const uint32_t lunAvail;
    const uint8_t UFSSlots;

    HCIMem UFSHCIMem;

    int readPendingNum;
    int writePendingNum;

    uint8_t activeDoorbells;
    uint8_t pendingDoorbells;

    uint32_t countInt;

    uint32_t transferTrack;
    uint32_t taskCommandTrack;

    Tick transactionStart[32];
    Tick idlePhaseStart;

    std::vector<UFSSCSIDevice*> UFSDevice;

    struct SCSIReply request_out_datain;

    struct SCSIResumeInfo SCSIInfo;

    std::deque<struct transferStart> transferEnd;

    std::deque<struct taskStart> taskInfo;
    std::deque<struct transferStart> transferStartInfo;

    std::deque<struct writeToDiskBurst> dmaWriteInfo;

    std::deque<struct transferInfo> SSDWriteinfo;

    std::deque<struct transferInfo> SSDReadPending;

    std::deque<struct UTPTransferReqDesc*> garbage;

    struct UFSHostDeviceStats stats;

    std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readDone> >
    readDoneEvent;
    std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::writeDone> >
    writeDoneEvent;

    Callback* transferDoneCallback;
    Callback* memReadCallback;

    EventWrapper<UFSHostDevice, &UFSHostDevice::SCSIStart> SCSIResumeEvent;

    EventWrapper<UFSHostDevice, &UFSHostDevice::finalUTP> UTPEvent;

    std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readGarbage> >
    readGarbageEventQueue;

    std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::taskStart> >
    taskEventQueue;
    std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::transferStart> >
    transferEventQueue;

    static const unsigned int UTPTransferREQCOMPL = 0x01;//UFS_BIT(0)
    static const unsigned int UTPTaskREQCOMPL = 0x200;//UFS_BIT(9)
    static const unsigned int UICCommandCOMPL = 0x400;//UFS_BIT(10)
    static const unsigned int UICCommandReady = 0x08;//UFS_BIT(3)

    /*
     * UFSHCI Registers; please refer to
     * http://www.jedec.org/standards-documents/results/jesd223
     * for their definition.
     */
    enum UFSHCIRegisters {
        regControllerCapabilities = 0x00,
        regUFSVersion = 0x08,
        regControllerDEVID = 0x10,
        regControllerPRODID = 0x14,
        regInterruptStatus = 0x20,
        regInterruptEnable = 0x24,
        regControllerStatus = 0x30,
        regControllerEnable = 0x34,
        regUICErrorCodePHYAdapterLayer = 0x38,
        regUICErrorCodeDataLinkLayer = 0x3C,
        regUICErrorCodeNetworkLayer = 0x40,
        regUICErrorCodeTransportLayer = 0x44,
        regUICErrorCodeDME = 0x48,
        regUTPTransferREQINTAGGControl = 0x4C,
        regUTPTransferREQListBaseL = 0x50,
        regUTPTransferREQListBaseH = 0x54,
        regUTPTransferREQDoorbell = 0x58,
        regUTPTransferREQListClear = 0x5C,
        regUTPTransferREQListRunStop = 0x60,
        regUTPTaskREQListBaseL = 0x70,
        regUTPTaskREQListBaseH = 0x74,
        regUTPTaskREQDoorbell = 0x78,
        regUTPTaskREQListClear = 0x7C,
        regUTPTaskREQListRunStop = 0x80,
        regUICCommand = 0x90,
        regUICCommandArg1 = 0x94,
        regUICCommandArg2 = 0x98,
        regUICCommandArg3 = 0x9C
    };
};

#endif //__DEV_ARM_UFS_DEVICE_HH__