An entry element for a vector clock versioning scheme This assigns the
version from a specific machine, the VectorClock keeps track of the complete
system version, which will consist of many individual Version objects.
Is this Reflexive, AntiSymetic, and Transitive? Compare two VectorClocks,
the outcomes will be one of the following: -- Clock 1 is BEFORE clock 2
if there exists an i such that c1(i) <= c(2) and there does not exist a j
such that c1(j) > c2(j).
Compare the current ports of this switch to the newPorts list and
return the changes that would be applied to transfort the current
ports to the new ports.
Create a title based on switch ID, portID, vlanID, and counterName
If portID is -1, the title represents the given switch only
If portID is a non-negative number, the title represents the port on the given switch
Create a title based on switch ID, portID, vlanID, counterName, and subCategory
If portID is -1, the title represents the given switch only
If portID is a non-negative number, the title represents the port on the given switch
For example: PacketIns can be further categorized based on L2 etherType or L3 protocol