Alaa R. Alameldeen

Patents

• Zhe Wang, Zeshan A. Chishti, Muthukumar P. Swaminathan, Alaa R. Alameldeen, Kunal A. Khochare, Jason A. Gayman, "Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memory," US Patent 10,452,312, October 22, 2019.

• Zhe Wang, Zeshan A. Chishti, Alaa R. Alameldeen, and Rajat Agarwal, "Near memory miss prediction to reduce memory access latency," US Patent 10,417,135, September 17, 2019.

• Zhe Wang, Chris Wilkerson, Zeshan A. Chishti, Seth H. Pugsley, Alaa R. Alameldeen, and Shih-Lien Lu, "Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory," US Patent 10,261,901, April 16, 2019.

• Zhe Wang, Chris Wilkerson, Zeshan A. Chishti, Seth H. Pugsley, Alaa R. Alameldeen, and Shih-Lien Lu, "Method and apparatus for pre-fetching data in a system having a multi-level system memory," US Patent 10,108,549, October 23, 2018.

• Alaa R. Alameldeen, Glenn J. Hinton, Blaise Fanning, and James J. Greensky, "Replacement of a Block with a Compressed Block to Increase Capacity of a Memory-Side Cache," US Patent 10,048,868, August 14, 2018.

• Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, and Jaewoong Sim, "Method and Apparatus for Implementing a Heterogeneous Memory Subsystem," US Patent 9,921,972, March 20, 2018.

• Alaa R. Alameldeen, Chris Wilkerson, Eugene Gorbatov, and Zeshan Chishti, "System and Method for Thread Scheduling on Reconfigurable Processor Cores," US Patent 9,703,708, July 11, 2017.

• Chris Wilkerson, Alaa R. Alameldeen, Zhe Wang, and Zeshan Chishti, "Multi-Level Memory Management," US Patent 9,583,182, February 28, 2017.

• Chris Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, and Jaewoong Sim, "Method and Apparatus for Implementing a Heterogeneous Memory Subsystem," US Patent 9,472,248, October 18, 2016.

• Chris Wilkerson, Alaa R. Alameldeen, Eugene Gorbatov, and Zeshan A. Chishti, "Systems and Methods for Managing Reconfigurable Processor Cores," US Patent 9,417,879, August 16, 2016.

• Tingting Sha, Chris Wilkerson, Herbert Hum, and Alaa R. Alameldeen, "Compiler Assisted Low Power and High Performance Load Handling Based on Load Types," US Patent 9,311,085, April 12, 2016.

• Alaa R. Alameldeen, Niranjan L. Cooray, Jayesh Gaur, Steven D. Pudar, Manuel A. Aguilar Arreola, Margareth E. Marrugo, and Chinnakrishnan Ballapuram, "Cache Memory Data Compression and Decompression," US Patent 9,292,449, March 22, 2016.

• Sreenivas Subramoney, Jayesh Gaur, and Alaa R. Alameldeen, "Data Compression in Processor Caches," US Patent 9,251,096, February 2, 2016.

• Alaa R. Alameldeen, Chris Wilkerson, and Samira M. Khan, "Read-Write Partitioning of Cache Memory," US Patent 9,233,710, December 29, 2015.

• Chris Wilkerson, Alaa R. Alameldeen, and Shih-Lien Lu, "Selective Error Correction in Memory to Reduce Power Consumption," US Patent 8,966,345, February 25, 2015.

• Muhammad M. Khellah, Chris Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, and Gunjan H. Pandya, "Reducing Minimum Operating Voltage through Hybrid Cache Design," US Patent 8,868,836, October 21, 2014.

• Alaa R. Alameldeen, Ilya Wagner, Zeshan A. Chishti, Wei Wu, and Chris Wilkerson, "Dynamically Allocatable Memory Error Mitigation," US Patent 8,806,285, August 12, 2014.

• Chris Wilkerson, Alaa R. Alameldeen, and Jaydeep P. Kulkarni, "Adaptive Self-Repairing Cache," US Patent 8,719,502, May 6, 2014.

• Chris Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Dinesh Somasekhar, Wei Wu, and Shih-Lien Lu, "Method and Apparatus for Using Cache Memory in a System that Supports a Low Power State," US Patent 8,640,005, January 28, 2014.

• Alaa R. Alameldeen and Zeshan A. Chishti, "Hardware Support for Thread Scheduling on Multi-Core Processors," US Patent 8.276,142, September 25, 2012.

• Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar, Muhammad Khellah, and Shih-Lien Lu, "Performing Multi-Bit Error Correction on a Cache Line," US Patent 8,245,111, August 14, 2012.

• David A. Wood and Alaa R. Alameldeen, "Adaptive Cache Compression System," US Patent 7,412,564, August 12, 2008.