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Research Areas
High-Performance Memory Architecture:
Memory is a critical performance bottleneck for many applications due to the large speed gap between processors and memory, i.e., the "memory wall." This research area focuses on improving the performance of the memory hierarchy using:
- Heterogeneous memory architecture to scale both memory capacity, speed, and bandwidth.
- Cache management policies that favor more critical read requests over write requests.
- Better memory performance by parallelizing refreshes with accesses.
- Processing in/near memory.
- Improving memory performance of machine learning workloads by reducing their memory footprint or by processing in/near memory.
Energy-Efficient Cache and Memory Architectures:
Power is a primary constraint in chip design as it limits potential performance improvements from frequency scaling. A key technique to reduce system power and energy is to reduce the operating voltage. However, reducing voltage causes a large number of cell failures in caches and memory. This research focuses on mechanisms and architectures to:
- Enable low voltage operation by avoiding cell failures or bypassing failing cells.
- Use strong Error-Correcting Codes (ECC) to improve reliability at low voltage.
- Use heterogeneous-cell cache architectures to enable cache low-voltage operation while preserving cache capacity.
Memory Reliability:
Architectural mechanisms to improve memory reliability.
Cache and Memory Compression:
Compression increases cache and/or memory capacity with little area cost. However, cache compression increases latency due to decompression even with no benefit, and could negatively impact cache replacement policies. Memory compression requires changing the operating system and increases memory traffic due to metadata and fragmentation. This research targets:
- Adaptive compression to avoid slowdown when compression has no benefit, or opportunistically compress blocks when there is benefit.
- Low latency hardware compression algorithms.
- OS-transparent hardware memory compression.
- New evaluation methodology for compression studies.
Simulation and Performance Evaluation:
Simulator development, and performance analysis of multi-threaded workloads. This research addresses variability in simulation results for multi-threaded workloads and demostrates the problems introduced when using common metrics like Instructions-Per-Cycle (IPC) to evaluate them. This research proposes mechanisms to reduce the impact of variability and use work-related metrics for performance evaluation.
Other Misc. Topics:
Other research on computer architecture, database systems, and computer vision.
For my graduate school research, please visit my old research page.
Publications by Research Area
High-Performance Memory Architecture
- Berkin Akin, Zeshan A. Chishti, Alaa R. Alameldeen, "ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions," 52nd International Symposium on Microarchitecture (MICRO-52), pages 126-138, Columbus, OH, USA, October 2019.
- Berkin Akin and Alaa R. Alameldeen, "A Case for Asymmetric Processing in Memory," IEEE Computer Architecture Letters, 18(1), pages 22-25, January-June 2019.
- Jagadish B. Kotra, Haibo Zhang, Alaa R. Alameldeen, Chris Wilkerson, Mahmut T. Kandemir, "Chameleon: A Dynamically Reconfigurable Heterogenous Memory System," 51st International
Symposium on Microarchitecture (MICRO-51), Fukuoka, Japan, October 2018.
- Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, and Hyesoon Kim, "Transparent Hardware Management of Stacked DRAM as Part of Memory," 47th International Symposium on Microarchitecture (MICRO-47), Cambridge, UK, Dec 2014.
- Samira M. Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, and Daniel A. Jiménez, "Improving Cache Performance by Exploiting Read-Write Disparity," 20th Annual International Symposium on High Performance Computer Architecture (HPCA-20), Orlando, FL, USA, February 2014.
- Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Chris Wilkerson, Alaa Alameldeen, Yoongu Kim, Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses," 20th Annual International Symposium on High Performance Computer Architecture (HPCA-20), Orlando, FL, USA, February 2014.
Energy-Efficient Cache and Memory Architectures
- Chris Wilkerson, Alaa R. Alameldeen, and Zeshan Chishti, "Scaling the Memory Reliability Wall,"Intel Technology Journal, Volume 17, Issue 1, 2013.
- Alaa R. Alameldeen, Nam Sung Kim, Samira M. Khan, Hamid Reza Ghasemi, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jiménez, "Improving Memory Reliability, Power, and Performance Using Mixed-Cell Designs," Intel Technology Journal, Volume 17, Issue 1, 2013.
- Samira M. Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jiménez, "Improving Multi-Core Performance Using Mixed-Cell Cache Architecture," 19th Annual International Symposium on High Performance Computer Architecture (HPCA-19), Shenzhen, China, February 2013.
- Amr Helmy and Alaa R. Alameldeen, "Redundancy and ECC Mechanisms to Improve Energy Efficiency of On-Die Interconnects," 3rd International Conference on Energy-Aware Computing, METU NCC, Cyprus, December 2012.
- Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, and Shih-Lien Lu, "Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes," 38th Annual International Symposium on Computer Architecture (ISCA-38), San Jose, CA, June 2011.
- Shih-Lien Lu, Alaa R. Alameldeen, Keith Bowman, Zeshan Chishti, Chris Wilkerson, and Wei Wu, "Architectural-Level Error-Tolerant Techniques for Low Supply Voltage Cache Operation," 2011 IEEE International Conference on IC Design & Technology (ICICDT 2011), Kaohsiung, Taiwan, May 2011.
- Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, and Shih-Lien Lu, "Adaptive Cache Design to Enable Reliable Low-Voltage Operation," IEEE Transactions on Computers, January 2011.
- Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, and Shih-Lien Lu, "Reducing Cache Power with Low-Cost, Multi-Bit Error-Correcting Codes," 37th Annual International Symposium on Computer Architecture (ISCA-37),Saint Malo, France, June 2010.
- Zeshan Chishti, Alaa R. Alamelden, Chris Wilkerson, Wei Wu and Shih-Lien Lu, "Improving Cache Lifetime Reliability at Ultra-Low Voltages," 42nd International Symposium on Microarchitecture (MICRO-42), New York City, NY, USA, December 2009.
- Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah and Shih-Lien Lu, "Trading Off Cache Capacity for Low Voltage Operation," IEEE Micro Top Picks from the 2008 Computer Architecture Conferences, January/February 2009.
- Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah and Shih-Lien Lu, "Trading Off Cache Capacity for Reliability to Enable Low Voltage Operation," 35th Annual International Symposium on Computer Architecture (ISCA-2008), Beijing, China, June 2008.
Memory Reliability
- Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, and Onur Mutlu, "Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content," 50th International Symposium on Microarchitecture (MICRO-50), Boston, MA, USA, October 2017.
- Elizabeth Reed, Alaa R. Alameldeen, Helia Naeimi, and Patrick Stolt, "Probabilistic Replacement Strategies for Improving the Lifetimes of NVM-Based Caches," 3rd International Symposium on Memory Systems (MEMSYS-2017), Washington, D.C., USA, October 2017.
- Samira Khan, Chris Wilkerson, Donghyuk Lee, Alaa R. Alameldeen, Onur Mutlu, "A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failure in DRAM," IEEE Computer Architecture Letters, 16(2), July-December 2017.
- Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu, "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study," ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Austin, Texas, June 2014.
Cache and Memory Compression
- Esha Choukse, Mattan Erez, Alaa R. Alameldeen, "Compresso: Pragmatic Main Memory Compression," 51st International Symposium on Microarchitecture (MICRO-51), Fukuoka, Japan, October 2018.
- Alaa R. Alameldeen and Rajat Agarwal, "Opportunistic Compression for Direct-Mapped DRAM Caches," 4th International Symposium on Memory Systems (MEMSYS-2018), Washington, D.C., USA, October 2018.
- Esha Choukse, Mattan Erez, Alaa R. Alameldeen, "CompressPoints: An Evaluation Methodology for Compressed Memory Systems," IEEE Computer Architecture Letters, 17(2), July-December 2018.
- Jayesh Gaur, Alaa R. Alameldeen, and Sreenivas Subramoney, "Base-Victim Compression: An Opportunistic Cache Compression Architecture," 43rd Annual International Symposium on Computer Architecture (ISCA-43), Seoul, South Korea, June 2016.
- Alaa R. Alameldeen and David A. Wood, "Interactions Between Compression and Prefetching in Chip Multiprocessors," 13th Annual International Symposium on High-Performance Computer Architecture (HPCA-13), Phoenix, AZ, February 2007.
- Alaa R. Alameldeen, "Using Compression to Improve Chip Multiprocessor Performance," Ph.D. dissertation, Computer Sciences Department, University of Wisconsin-Madison, March 2006.
- Alaa R. Alameldeen and David A. Wood, "Adaptive Cache Compression for High-Performance Processors," 31st Annual International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004.
- Alaa R. Alameldeen and David A. Wood, "Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches," Dept. of Computer Sciences Technical Report CS-TR-2004-1500, April 2004.
Simulation and Performance Evaluation
- Alaa R. Alameldeen and David A. Wood, "IPC Considered Harmful for Multiprocessor Workloads," IEEE Micro Special Issue on Computer Architecture Simulation and Modeling, July/August 2006.
- Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood, "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News (CAN), September 2005.
- Alaa R. Alameldeen and David A. Wood, "Addressing Workload Variability in Architectural Simulations," IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, November-December 2003.
- Alaa R. Alameldeen and David A. Wood, "Variability in Architectural Simulations of Multi-threaded Workloads," 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA, February 2003.
- Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood, "Simulating a $2M Commercial Server on a $2K PC," IEEE Computer, February 2003.
- Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood, "Evaluating Non-deterministic Multi-threaded Commercial Workloads," 5th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-02), Cambridge, MA, February 2002.
Other Misc. Topics
- Alaa R. Alameldeen, "Guest Editor's Introduction: The first JILP Data Prefetching Championship," Journal of Instruction Level Parallelism, Volume 13, 2011.
- Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris B. Wilkerson, "Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors," IEEE Transactions on Very Large Scale Integration Systems, December 2009.
- Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan and Chris B. Wilkerson, "Impact of Die-to-Die and Within-Die Parameter Variations on the Throughput Distribution of Multi-Core Processors," 12th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-2007), Portland, OR, August 2007.
- Ashraf Aboulnaga, Alaa R. Alameldeen, and Jeffrey F. Naugton, "Estimating the Selectivity of XML Path Expressions for Internet Scale Applications," 27th International Conference on Very Large Data Bases (VLDB-27), Rome, Italy, September 2001.
- Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood, "Timestamp Snooping: An Approach for Extending SMPs," 9th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Cambridge, MA, Nov. 2000.
- Alaa R. Alameldeen and M. A. Ismail, "Sequential Methods for Recovering Structure and Motion of a Rigid Object from an Image Sequence," Proc. 3rd International Conference on Computer Vision, Pattern Recognition and Image Processing (CVPRIP2000), Atlantic City, NJ, Feb-Mar 2000.
- Alaa R. Alameldeen, "Sequential Methods for Recovering Structure and Motion of a Rigid Object from an Image Sequence," Master thesis, Department of Computer Science and Automatic Control, Faculty of Engineering, Alexandria University, July 1999.
Please visit my Google Scholar page for a more up-to-date list.
Last modified:
by Alaa R. Alameldeen.
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