Computer Sciences Dept. UW Computer Sciences

Alaa R. Alameldeen

Research Areas

High-Performance Memory Architecture: Memory is a critical performance bottleneck for many applications due to the large speed gap between processors and memory, i.e., the "memory wall." This research area focuses on improving the performance of the memory hierarchy using:

  • Heterogeneous memory architecture to scale both memory capacity, speed, and bandwidth.
  • Cache management policies that favor more critical read requests over write requests.
  • Better memory performance by parallelizing refreshes with accesses.
  • Processing in/near memory.
  • Improving memory performance of machine learning workloads by reducing their memory footprint or by processing in/near memory.

Energy-Efficient Cache and Memory Architectures: Power is a primary constraint in chip design as it limits potential performance improvements from frequency scaling. A key technique to reduce system power and energy is to reduce the operating voltage. However, reducing voltage causes a large number of cell failures in caches and memory. This research focuses on mechanisms and architectures to:

  • Enable low voltage operation by avoiding cell failures or bypassing failing cells.
  • Use strong Error-Correcting Codes (ECC) to improve reliability at low voltage.
  • Use heterogeneous-cell cache architectures to enable cache low-voltage operation while preserving cache capacity.

Memory Reliability: Architectural mechanisms to improve memory reliability.

Cache and Memory Compression: Compression increases cache and/or memory capacity with little area cost. However, cache compression increases latency due to decompression even with no benefit, and could negatively impact cache replacement policies. Memory compression requires changing the operating system and increases memory traffic due to metadata and fragmentation. This research targets:

  • Adaptive compression to avoid slowdown when compression has no benefit, or opportunistically compress blocks when there is benefit.
  • Low latency hardware compression algorithms.
  • OS-transparent hardware memory compression.
  • New evaluation methodology for compression studies.

Simulation and Performance Evaluation: Simulator development, and performance analysis of multi-threaded workloads. This research addresses variability in simulation results for multi-threaded workloads and demostrates the problems introduced when using common metrics like Instructions-Per-Cycle (IPC) to evaluate them. This research proposes mechanisms to reduce the impact of variability and use work-related metrics for performance evaluation.

Other Misc. Topics: Other research on computer architecture, database systems, and computer vision.

For my graduate school research, please visit my old research page.

Publications by Research Area

High-Performance Memory Architecture

Energy-Efficient Cache and Memory Architectures

Memory Reliability

Cache and Memory Compression

Simulation and Performance Evaluation

Other Misc. Topics

Please visit my Google Scholar page for a more up-to-date list.

Last modified: by Alaa R. Alameldeen.

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