Quals Reading List

• Joseph A. Fisher and B. Ramakrishna Rau. Instruction-Level Parallel Processing. Science, 13 Sep 1991, pp.1233-1241. Review
• Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers, Proc. of International Symposium on Computer Architecture, June 1990, 364-373.
• Randy H. Katz, Garth A. Gibson, and David A. Patterson. Disk System Architectures for High Performance Computing, Proc. of the IEEE, Dec 1989, pp. 1842-1858 Notes
• Scott A. Mahlke, Richard E. Hank, James E. McCormack, David I. August, and Wen-mei W. Hwu. A comparison of Full and Partial Predicated Execution Support for ILP processors, Proc. International Symposium of Computer Architecture, June 1995. pp 138-150 Review
• James Montanaro et. al, A 160-MHz, 32-b, 0.5-W, CMOS RISC Microprocessor, IEEE Journal of Solid-State Circuits, November 1996, pp. 1703-1714. Review
• Subbarao Palacharla, Norman P. Jouppi and J. E. Smith. Complexity-effective Superscalar Processors, Proc. of the 24th Annual International Symposium on Computer Architecture , June 1997, pp. 206-218. Review
• C. Ruemmler and J. Wilkes. An introduction to Disk Drive Modeling, IEEE Computer , March 1994, pp. 17-28. Notes
• Richard M. Russell. The Cray-1 Computer System, Communications of the ACM , Jan 1978, pp. 63-72. Notes
• Timothy J. Slegel et. al. IBM's S/390 G5 Microprocessor, IEEE MICRO, Mar/Apr 1999, pp. 12-23. Notes
• J. E. Smith and A. R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers , May 1998, pp. 562-573.
• Gurindar S. Sohi and S. Vajapeyam, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers , March 1990, pp.349-355
• Madhusudhan Talluri and Mark D. Hill. Surpassing the TLB Performance of Superpages with Less Operating System Support. Proc. of International Conference on Architectural Support for Programming Languages and Operating Systems, October 1994, pp. 171-182. Review
• Wen-Hann Wang, Jean-Loup Baer and Henry M. Levy, Organization and Performance of a Two-level Virtual-Real Cache Hierarchy, Proc. International Symposium on Computer Architecture June 1989, pp. 140-148 Review
• William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981, pp. 41-48.Notes
• Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro , April 1996, pp. 28-40. Notes
• T-Y. Yeh and Y. Patt, Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, November 1991, pp. 51-61. Review
• Sarita V. Adve and Kourosh Gharachorloo. Shared Memory Consistency Models: A Tutorial, IEEE Computer, December 1996, pp. 66-76.Notes
• W. Daniel Hillis and Guy L. Steele. Data Parallel Algorithms, Communications of the ACM, December 1986, pp. 1170-1183. Notes