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Trace Table (problem 2) Print this table and fill in the values by hand and turn it in with your submission. Run each trace using mem_system_perfbench. Determine when the events listed in the table occur and write down the cycle number. This should be an in integer and should be the DUT/clkgen/cycle_count signal. This is NOT the raw simulation time that vsim shows you. The first row is filled up as 3 because I am assuming your cache can accept a request in the cycle immediately after reset, which is cycle 3 in our testbench.
These trace files should already be in your download tarball for HW5.
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