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UW-Madison
Computer Sciences Dept.

CS/ECE 752 Advanced Computer Architecture I Fall 2008 Section 1
Instructor David A. Wood and T. A. Khai Tran
URL: http://www.cs.wisc.edu/~david/courses/cs752/Fall2008/

Reader 1

This reader may still change slightly, and, if so, I will send email notice of changes.

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Fourth Edition, 2007.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

  • Readings that start with a bullet (like this entry) will have reviews due before class.

    Technology, Cost, Performance, Power, etc.

    H&P Chapter 1.

  • Gordon E. Moore, Cramming More Components onto Integrated Circuits, Electronics, April 1965. Reprinted in HJ&S pp. 56-59.

    ITRS Roadmap -- Executive Summary, Go to URL http://www.itrs.net/Links/2005ITRS/Home2005.htm and click on Executive Summary, 89 pages. Read Introduction (pp. 1-10) and flip through Grand Challenges (pp. 11-18), reading, at least, titles. Study the trends in the Overall Roadmap Technology Characteristics (pp. 59-85). Don't try to memorize the tables. Rather, identify key facts and trends. Such as "what is the overall scaling trend?" and "what is the target yield range for volume production?".

  • David A. Patterson, Latency lags bandwith, Communications of the ACM, October 2004. Online PDF for University of Wisconsin only.

    Standard Performance Evaluation Corporation (SPEC). URL: http://www.specbench.org/. Read the "run and reporting rules" for SPEC CPU2006 and SPEC jAppServer2004. You may skim the rest of the web site.

    Transaction Processing Council (TPC). URL: http://www.tpc.org (reference).

    Instruction Sets

    H&P Appendix B.

  • Burger et al. Scaling to end of Silicon with EDGE architectures. IEEE Computer, July 2004. PDF download.

    William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981. Reprinted in HJ&S pp. 119-125. Reference

  • Colwell, R.P.; Hitchcock, C.Y., III; Jensen, E.D.; Brinkley Sprunt, H.M.; Kollar, C.P., "Instruction Sets and Beyond: Computers, Complexity, and Controversy," Computer , vol.18, no.9, pp.8-19, Sept. 1985
    URL: http://ieeexplore.ieee.org/iel5/2/34809/01663000.pdf?isnumber=34809&prod=JNL&arnumber=1663000&arnumber=1663000&arSt=8&ared=19&arAuthor=Colwell%2C+R.P.%3B+Hitchcock%2C+C.Y.%2C+III%3B+Jensen%2C+E.D.%3B+Brinkley+Sprunt%2C+H.M.%3B+Kollar%2C+C.P.

    Reprinted in HJ&S pp. 144-155.

  • J. S. Emer and D. W. Clark. A Characterization of Processor Performance in the VAX-11/780, Proc. International Symposium on Computer Architecture , June 1984. Reprinted in HJ&S pp. 101-110.

    IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1: Basic Architecture. Online PDF for University of Wisconsin only., 476 pages (reference).

    Pipelining

    H&P Appendix A reviews the pipelining material taught in CS/ECE 552. If you have taken a similar course elsewhere, make sure that you are very comfortable with this material.

  • Hartstein and Puzak, Optimum Power/Performance Pipeline Depth, MICRO 2003. PDF download

  • Dan Ernst, et al., A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proc. 36th Annual International Symposium on Microarchitecture, 2003 Online PDF for University of Wisconsin only.

    Hrishikesh et al., The Optimum Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays, ISCA 2002. PDF download Reference reading

    Dynamic Scheduling

    H&P Chapter 2 (except 2.7) and 3

  • T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, Nov 1991. Reprinted in HJ&S pp. 228-237.

  • Seznec, A., Felix, S., Krishnan, V., and Sazeides, Y. Design tradeoffs for the alpha EV8 conditional branch predictor. ISCA 2002. IEEE Xplore link

  • Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro, April 1996. Reprinted in HJ&S pp. 275-287.

  • Gurindar S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, Proc. 14th Annual Symposium in Computer Architecture, June 1987 (reference). Reprinted in HJ&S pp. 244-251.

  • J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988. Reprinted in HJ&S pp. 202-213.

  • Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi, Dynamic Speculation and Synchronization of Data Dependences. ISCA 1997: 181-193 ACM Digital Library -- On Campus Only

    D. Papworth. Tuning the Pentium Pro Architecture, IEEE Micro, April 1996. Reprinted in HJ&S pp. 660-667.

    E. Borch, E. Tune, S. Manne, and J. Emer, Loose Loops Sink Chips, Proceedings of HPCA-8, February 2002. Online PDF for University of Wisconsin only.

    Simcha Gochman, Ronny Ronen, Ittai Anati, Ariel Berkovits, Tsvika Kurts, Alon Naveh, Ali Saeed, Zeev Sperber, Robert C. Valentine, The Intel (R) Pentium(R) M Processor: Microarchitecture and Performance Intel Technology Journal, May 2003. Online PDF.

    Onur Mutlu and Jared Stark and Chris Wilkerson and Yale N. Patt, Runahead Execution: An Effective Alternative to Large Instruction Windows, IEEE Micro, Nov/Dec 2003. Online PDF for University of Wisconsin only.

    Srikanth Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, and Mike Upton, Continual Flow Pipelines, Proceedings of ASPLOS 2004, October 2004. Online PDF for University of Wisconsin Only.

     

    Miscellaneous

    Arthur W. Burks, Herman H. Goldstine, John von Neumann. Preliminary discussion of the logical design of an electronic computing instrument, Report to the U.S. Army Ordinance Department, 1946. Reprinted as Chapter 4 of Bell and Newell, Computer Structures: Readings and Examples, McGraw-Hill, 1971. URL: Chapter 4 of http://www.research.microsoft.com/users/gbell/Computer_Structures__Readings_and_Examples/ (reference).

    Timothy J. Slegel, et al., IBM's S/390 G5 Microprocessor, IEEE Micro, Mar/Apr 1999, Online PDF for University of Wisconsin only.

    Multiple Issue and Static Scheduling

    H&P Chapter 2.7

  • C. McNairy and D. Soltis, Itanium 2 Processor Microarchitecture, IEEE Micro, Mar-Apr 2003, pp. 44-55. Online PDF for University of Wisconsin only.

    Intel (R) Itanium (R) Architecture Software Development Manual, URL: http://www.intel.com/design/itanium/manuals/iiasdmanual.htm. See especially Volume 1's (Application Architecture) Chapter 4 (Application Programming Model), 36 pages (reference).

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