Computer Sciences Dept.

CS/ECE 758 Advanced Topics in Computer Architecture

Programming Current and Future Multicore Processors

Fall 2007 Section 1
Instructor David A. Wood and T. A. Dan Gibson
URL: http://www.cs.wisc.edu/~david/courses/cs758/Fall2007/

The Problem

Multicore processors are here and coming fast! Intel is currently shipping their quad-core Cloverdale processors, with AMD promising their quad-core Barcelona processor later this year. Sun is shipping the 8-core, 32-thread Niagara processors and has announced that their forth-coming Rock processor will have 16 cores. Furthermore, Intel recently demonstrated an experimental 80-core chip. The rapid shift to multicore processors promises to transform the raw computing power of desktop and server computers.

But how will we program these machines? Very few people have any real experience programming multiprocessor systems. Furthermore, shared-memory parallel programming is a "known hard problem," due to deadlocks, data races, prioity inversions, etc. Are there new programming languages, models, and/or libraries that can make this easier? Is transactional memory the silver bullet that will make parallel programming easy? What do application programmers need (that computer architects can provide) to make parallel programming easier?

  AMD Barcelona chip

In this course, we will work together to explore these questions. During the first half of the semester, we will study and write programs for both current and proposed future machines. Homework will include writing programs using P-threads, OpenMP, Cilk, and the TL2 Software Transactional Memory (STM) for the quad-core Intel Cloverdale and the 32-thread Sun Niagara. You will also write programs for the Wisconsin LogTM and Stanford TCC systems, which "implement" Hardware Transactional Memory HTM) using software simulations. For the second half of the semester, students will work in small groups to parallelize larger applications targeting future multi-core chips. Ideally, these applications will form the basis of a new parallel benchmark suite.

The Students

My goal is to bring together computational and computer scientists who are interested in learning about and perhaps advancing the state-of-the-art in programming multicore processors. Prospective students should have ONE of the following:

  • Substantial programming experience, ideally on a computationally-intensive single-threaded application that you would like to parallelize,
  • At least one 700-level course in either architecture, programming languages, or operating systems,
  • Instructor's consent.

When and Where

    Tuesdays and Thursdays, 1:00pm--2:15pm
    1289 Computer Sciences and Statistics

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