Dan Gibson Note: I have graduated and moved on. This page is no longer up-to-date. Dan Gibson on Google Sites.

Research Summary

My thesis work (here) explores the power/performance tradeoffs in future CMPs. Much of my work has focused on a scalable core design, called Forwardflow, which implements out-of-order execution using dynamically scalable hardware. Interested readers can look at my Forwardflow TR, or my Forwardflow ISCA paper, linked below.

Dan Gibson and David A. Wood. Forwardflow: A Scalable Core for Power-Constrained CMPs International Symposium on Computer Architecture (ISCA), June 2010. Paper: PDF         BibTeX: BibTeX         Talk: PPT

Dan Gibson and David A. Wood. Forwardflow: Scalable, RAM-Based Dataflow Execution University of Wisconsin-Madison Computer Sciences Technical Report #TR1656-2009. May 2009. Paper: PDF         BibTeX: BibTeX

Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, and Mikko H. Lipasti Achieving predictable performance through better memory controller placement in many-core CMPs International Symposium on Computer Architecture (ISCA), June 2009. Paper: PDF         BibTeX: BibTeX         Talk: Diamonds are an Architect's Best Friend

I also participated in a project with Randy Smith and Shijin Kong, reflecting on how parallel (software) packet classification algorithms run on today's modern CMPs as compared to the semi-antiquated SMPs of yesteryear.

Randy Smith, Dan Gibson, and Shijin Kong. To CMP or not to CMP: Analyzing Packet Classification on Modern and Traditional Network Processors (Poster Session) Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems. 2007. Paper: PDF

Randy Smith, Dan Gibson, and Shijin Kong. To CMP or not to CMP: Analyzing Packet Classification on Modern and Traditional Network Processors University of Wisconsin-Madison Computer Sciences Technical Report #TR1652-2009. April 2009. Paper: PDF         BibTeX: BibTeX

In the Summer and Fall of 2005, I implemented a memory consistency checker for our simulation infrastructure, GEMS. Although GEMS uses Simics for functional simulation and memory consistency (and is therefore sequentially consistent) we also wish to verify that our processor and protocol simulators accurately model sequential consistency timing characteristics. The consistency checker monitors the state of the simulator, ensuring that the timings reported by GEMS are not in violation if sequential consistency.

My previous work in Multifacet was in performance optimization of Ruby, our memory timing model.

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