Homework 6

(printable version)

  1. (4 points total) The processor has just entered the kernel as the result of an exception and the system registers have the following contents:
    • Cause 0x0000041c
    • Status 0x0000fb0c

    A. (2 points) What was the event that caused the exception?

    B. (2 points) What mode (user or kernel) was the processor in at the time of the exception?

  2. (5 points) The two representations (given in hexadecimal) 0xfe7a0004 and 0xfefa0007 are IEEE single precision floating point numbers. Show all work in adding the two numbers. Give the result both in binary and in hexadecimal and use round to nearest for rounding.

    Perform the following floating point operations on each pair of two 32-bit IEEE single precision values. Put the result in hexadecimal. If the result does not fit in the 32-bit standard, then use the rounding method specified for each operation. You must show your work (intermediate results) in order to receive full credit.

  3. (3 points) Use "round to + infinity" to approximate the result of this subtraction. 
    
       0x46a210a8 
     - 0x4ac60700 
     ------------

  4. (3 points) Use "round to zero" to approximate the result of this multiplication. 
    
       0x46a210a8 
     * 0x4ac60700 
     ------------
  5. (3 points) Use "round to nearest" to approximate the result of this division. 
    
        0x4ac60700  
      / 0x46a210a8  
      ------------

  6. (5 points) In a 3 stage pipeline with the following stages:

    1. Fetch and Update
    2. Load Operands
    3. Execute and Store

    How many stall cycles, if any, would occur in the following instruction sequence?
    • add $10, $8, $9
    • sw $10, 4($11)

  7. (10 points) Diagram the pipeline steps to execute the following MIPS RISC code. Use the 5-stage pipeline described in chapter 13. (You may use figures 13.2 and 13.3 as examples of pipeline diagrams.) 
    
add  $t0, $t1, $t2
addi $t3, $t0, 5
sll  $t6, $t8, $t2
  8. (3 points) Give a sequence of TAL instructions (2 or 3 instructions) that would have a control dependency in the 3 stage pipeline described above.

    • beqz $8, label
    • sub $9, $9, $11

    Assumes there is no delay branch implementation.


  9. (4 points) A computer system has one cache, called L1. Assume the following cache access parameters to show the work in calculating the average memory access time (AMAT) for this computer system.
    • TL1 is 20 nsec
    • Tmain memory is 1000 nsec
    • 94.6% of all memory requests hit in the L1 cache.

  10. (4 points) A direct mapped cache has 4K lines, and 8 32-bit words per block. How many bytes of data does this cache hold? How many bits of the address must be used to determine the line number? For a byte addressable machine, how many bits of address must be used to determine the byte within a block? If addresses are 32 bits, how many bits should be used for a tag?

  11. (2 points) How many valid bits would be needed in a cache with 4 lines (frames) and room for 4 blocks of data per line if each block of data is 256 bytes?

  12. (4 points) Describe what could go wrong if each of these steps were (individually) ommitted from the hardware that gets exception handling going:
    1. Set ExcCode in the Cause Register.
    2. Change to kernel mode.
    3. Disable further interrupts.
    4. Save current value of the PC in the EPC.

  13. (3 points) A program is executed to see how long it takes to run. It takes 30 seconds. The program is then improved, so that it only takes 20 seconds to execute the program, what speedup has been achieved? If the code within the program that was enhanced accounted for 80% of the original execution time of the program, what speedup was attained on this enhanced portion of code?

    Solution