Reseach Experience
June 2009-2014: UW-Madison, Research Assistant, WISCAL Group
Currently working on power reduction technique by exploiting adaptive voltage positioning optimized for multicore processors.
Designed and developed a core and resource scaling technique to improve power efficiency of high performance, power constrained multicore processors.
Designed and developed a cost-effective per-core DVFS for high performance, power-constrained multi-core processors by exploiting LDO regulators.
Designed and developed a low voltage on-chip cache architecture using heterogeneous cell size for high performance processors.
Contributed in area optimization of ultralow voltage SRAM with sizing, redundancy, and error correction codes.
Contributed in workload adaptive process tuning for power efficient multicore processors.
June 2007-July 2008: University of Tehran, Research Assistant, Multimedia Processing Laboratory under supervision of Professor Mahmoud Reza Hashemi:
Worked as a hardware and system designer in hardware implementation of H.264 encoder project.
Designed a memory hierarchy to handle memory requirement of different modules of H.264 encoder.
September 2001-June 2007: University of Tehran, Research Assistant, CAD Group under supervision of Professor Zainalabedin Navabi.
Head of an event-driven simulator project: To provide an environment for mixed signal, mixed domain, mixed language simulation.
Contributed in research, design, development, and verification of mixed signal simulator consisting of SystemC, VHDL, VHDL-AMS and Verilog compilers and simulators.
Contributed in research and development of two object oriented intermediate formats for compilers and simulator.
September 2003- September 2004: University of Tehran, Research Assistant:
Contributed in design and implementation of an instruction level simulator for a multi-threaded multi-issue VLIW stream processor (MISP).