Karthikeyan Sankaralingam's Publications
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A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems
Stephen W. Keckler, Doug Burger, Charles R. Moore, Ramadass Nagarajan, Karthikeyan Sankaralingam, Vikas Agarwal, M.S. Hrishikesh, Nitya Ranganathan, and Premkishore Shivakumar. A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems. In Proceedings of the 2003 International Solid-State Circuits Conference, pp. , February 2003.
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Abstract
This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15 times/ more instructions per clock than conventional superscalar architectures.
Additional Information
This is a test of the extra info broadcasting system.
BibTeX
@InProceedings{isscc03,
author = "Stephen W. Keckler and Doug Burger and Charles R. Moore and Ramadass Nagarajan and Karthikeyan Sankaralingam and Vikas Agarwal and M.S. Hrishikesh and Nitya Ranganathan and Premkishore Shivakumar",
title = "{A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems}",
pages = {},
booktitle = "Proceedings of the 2003 International Solid-State Circuits Conference",
year = 2003,
month = {February},
abstract={
This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15 times/ more instructions per clock than conventional superscalar architectures.},
bib2html_dl_html = "http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=27661&arnumber=1234252&count=236&index=56",
bib2html_pubtype = {Refereed Conference},
bib2html_rescat = {Architecture,Hardware},
bib2html_extra_info = {This is a test of the extra info broadcasting system.}
}
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