Computer Sciences Dept.

CS 838 Pervasive Parallelism Fall 2005 Section 3
Instructor Mark D. Hill

Future computer performance advances are between a rock (slow memory) and a hard place (multithreading). CS 838 Section 3 is about us teaching each other about this dilemma and then doing something about it.

The Problem

Society has come to expect repeated doubling of computer performance, inaccurately called Moore's Law. This growth occurs from a synergy of the real Moore's Law (doubling transistors per chip) and computer architecture innovations that profitably use those transistors. While the real Moore's Law will continue for a decade or more, I predict that the popular Moore's Law will end much sooner. This is because architects are hitting a rock due to memory accesses taking 100s of instruction opportunities.

To revitalize the popular Moore's Law, we must redefine it to look beyond thread performance to multithreaded performance. To this end, we can build chip multiprocessors (CMPs) with many processors per chip. CMPs will soon be an inflection point in server markets, where multithreaded workloads abound.

Unfortunately, many important workloads are single-threaded. Future performance doubling for these workloads will require going to the hard place of making the workloads effectively use CMP hardware. While computer architects can help, ultimately we must rethink computer science to move thread parallelism from the fringe to the center of our discipline.

The Students

My goal is to immerse students across computer science in pervasive parallel so that we can teach each other. I know know a lot about parallel architecture; you may know more about programming than me. Prospective students should have:
  • Done substantial programming (single-threaded is fine).
  • Taken a 700-level CS course in either architecture, operating systems, or networking.
  • Taken a second 700-level CS or ECE course.
  • Instructor's consent.

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