CS 838 Pervasive Parallelism Fall 2005 Section 3
Instructor Mark D. Hill
URL: http://www.cs.wisc.edu/~markhill/cs838/Fall2005/

Likely to be updated.

Background

John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002. From Chapter 6 Multiprocessors and Thread-Level Parallelism, pp. 528-664:

1. Introduction (read now)
2. Characteristics of Application Domains (read now)
3. Symmetric Shared-Memory Architectures (read now)
4. Performance of Symmetric Shared-Memory Multiprocessors (skim now; read later)
5. Distributed Shared-Memory Architectures (read now)
6. Performance of Distributed Shared-Memory Architectures (skim now; read later)
7. Synchronization (read now)
8. Models of Memory Consistency: An Introduction (optional)
9. Multithreading: Exploiting Thread-Level Parallelism within a Processor (read now)
10. Crosscutting Issues (optional)
11. Putting It All Together: Sun's Wildfire Prototype (optional)
12. Another View: Multithreading in a Commercial Server (optional)
13. Another View: Embedded Multiprocessors (optional)
14. Fallacies and Pitfalls (read now)
15. Concluding Remarks (read now)
16. Historical Perspective and References (skim now; read later)

Introduction

Herb Sutter, The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software, Dr. Dobb's Journal, 30(3), March 2005. Html.

Introduction to Parallel Computing LLNL Web Site (html). Reference.

Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29. Online PDF for University of Wisconsin only.

Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Mike Chen, and Kunle Olukotun, The Stanford Hydra CMP, IEEE Micro, March-April 2000, pp. 71-84. Online PDF for University of Wisconsin only.

Luiz Andre Barroso, et al., Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing, Proc. International Symposium on Computer Architecture, June 2000, pp. 282-293. Online PDF for University of Wisconsin only. Reference.

David A. Wood and Mark D. Hill, Cost-Effective Parallel Computing, IEEE Computer, February 1995. Final Scanned PDF or Near-Final Latex PDF. Reference.

Herb Sutter and James Larus, Software and the Concurrency Problem, ACM Queue, September 2005, Online PDF for University of Wisconsin only.

Make Way for Multiprocessors, ACM Queue, September 2005 Special Issue, Online PDF for University of Wisconsin only. Reference.

Programming

The Message Passing Interface (MPI) Tutorial LLNL Web Site (html).

The Message Passing Interface (MPI) Standard, ANL Web Site (html). Reference.

Message Passing Interface (MPI) Documentation, ANL Web Site (html). Reference.

Luiz Andre Barroso, Jeffrey Dean, Urs Holzle, Web Search For a Planet: The Google Cluster Architecture, IEEE Micro, 23(2):22-28, March-April 2003. Online PDF for University of Wisconsin only. Reference.

POSIX Threads Programming, Web Site (html). Reference.

Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta, The SPLASH-2 Programs: Characterization and Methodological Considerations, Proc. International Symposium on Computer Architecture, June 1995. Online PDF for University of Wisconsin only.

John M. Mellor-Crummey and Michael L. Scott, Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors ACM Trans. on Computer Systems. February 1991, pp. 21-65. Online PDF for University of Wisconsin only.

Thomas E. Anderson, Brian N. Bershad, Edward D. Lazowska, Henry M. Levy, Scheduler Activations: Effective Kernel Support for the User-level Management of Parallelism, Proc. Symposium on Operating System Principles, October 1991. Online PDF for University of Wisconsin only.

Atul Adya, Jon Howell, Marvin Theimer, Bill Bolosky, John Douceur, Cooperative Task Management without Manual Stack Management, or Event-driven Programming is not the Opposite of Threaded Programming, Proc. USENIX, June 2002. Online PDF for University of Wisconsin only. Reference.

LLNL OpenMP Tutorial, Web Site (html).

OpenMP: Simple, Portable, Scalable SMP Programming, Web Site (html). Reference.

Transactional Memory

Transactional Memory Online, Web Site (html). Reference.

Maurice Herlihy and J. Eliot B. Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures, Proc. International Symposium on Computer Architecture, May 1993. Online PDF for University of Wisconsin only.

Albert Chang and Mark F. Mergen, 801 Storage: Architecture and Programming, ACM Trans. on Computer Systems, February 1988. Online PDF for University of Wisconsin only. Concentrate on transactional issues (e.g., Section 3.3).

Ravi Rajwar and James R. Goodman, Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, Proc. 34th Intl. Symposium on Microarchitecture, December 2001. Online PDF for University of Wisconsin only.

Ravi Rajwar and James R. Goodman, Transactional Lock-Free Execution of Lock-Based Programs, Proc. Architectural Support for Programming Languages and Operating Systems, October 2002. Online PDF for University of Wisconsin only.

Virendra J. Marathe and Michael L. Scott, A Qualitative Survey of Modern Software Transactional Memory Systems, University of Rochester Computer Science Department TR 839, June 2004. Online PDF for University of Wisconsin only.

Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun, Transactional Memory Coherence and Consistency, Proc. International Symposium on Computer Architecture, June 2004. Online PDF for University of Wisconsin only.

Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben Hertzberg, Mike Chen, Christos Kozyrakis, and Kunle Olukotun, Programming with Transactional Coherence and Consistency (TCC), Proc. Architectural Support for Programming Languages and Operating Systems, October 2004. Online PDF for University of Wisconsin only. Reference.

Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood, LogTM: Log-based Transactional Memory, Submitted to Proc. Symposium on High-Performance Computer Architecture, February 2006. Online PDF.

C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, Unbounded Transactional Memory, Proc. Symposium on High-Performance Computer Architecture, February 2005. Online PDF for University of Wisconsin only.

Ravi Rajwar, Maurice Herlihy, and Konrad Lai, Virtualizing Transactional Memory, Proc. International Symposium on Computer Architecture, June 2005. Online PDF for University of Wisconsin only.

Maurice Herlihy, Victor Luchangco, and Mark Moir, Obstruction-Free Synchronization: Double-Ended Queues as an Example Proc. International Conference on Distributed Computing Systems, Online PDF for University of Wisconsin only. Reference.

Liblit Lecture (Post-Exam)

Tim Harris, Design Choices for Language-based Transactions, Microsoft Techical Report UCAM-CL-TR-572, August 2003. PDF.

Carlstrom et al., Transactional Execution of Java Programs, OOPSLA Workshop on Synchronization and Concurrency in Object-Oriented Languages (SCOOL), October 2005. PDF.

Students Present

As students present papers, these paper will be assigned for reading.