Project Overview
Emerging load-store interconnects, such as CXL and UALink, are transforming communication within and across computing systems. They no longer simply connect devices; instead, they serve as the communication fabric for memory/storage/accelerator pooling. However, today’s systems continue to treat these interconnects as opaque hardware, providing little visibility, programmability, or traffic control.
The SD-LSI (Software-Defined Load-Store Interconnect) project revisits load-store interconnects via the lens of software-defined networking. Rather than treating them as fixed hardware buses, we apply networking principles to understand, profile, and optimize end-to-end communication over load-store fabrics. Our goal is to give software greater visibility and control over communication, enabling predictable latency, efficient bandwidth utilization, fair resource sharing, and high-performance composable systems within and across hosts.
Challenges
Load-store interconnects have become the underlying fabric for composing memory, storage, and accelerators into host-native resource pools. However, they only expose limited communication capabilities at the transaction layer, leading to the following challenges:
- Limited observability. Communication spans CPUs, memory hierarchies, I/O fabrics, switches, and devices, yet the interconnect exposes little end-to-end visibility for profiling, diagnosis, and optimization.
- No traffic control. Load/store traffic is generated implicitly by device execution, leaving little capability to manage latency, bandwidth, fairness, or quality of service.
- Opaque communication behavior. Proprietary protocols, deep microarchitectural pipelines, and hardware scheduling obscure communication bottlenecks, resource contention, and performance anomalies.
- Multi-tenancy. As load-store interconnects evolve into switched fabrics, multiple applications compete for shared communication resources without effective isolation or predictable performance.
Our Approach
Our insight is that load-store interconnects should expose software-defined communication capabilities to software. We ask: How can networking principles be applied to understand, profile, virtualize, and optimize end-to-end communication over emerging load-store interconnects? In this project, we have developed systems for communication characterization, end-to-end profiling, communication virtualization, and traffic management across composable infrastructures, enabling predictable, efficient, and scalable load-store communication for resource pooling systems.
Here are the systems we have built.
- MemChannel develops a CSFQ-inspired transport layer for switched CXL memory pooling (NSDI’26).
- PathFinder tracks and analyzes
CXL.memusing Intel PMUs (SIGCOMM’25). - MegaStation realizes the MIMO baseband processing on a single-node supercomputer (NSDI’25).
- rPCIeBench develops a benchmarking framework to characterize Routable PCIe (NSDI’24).
- FCC proposes a new computing paradigm for composable infrastructure (HotOS’23).