rAMANATHAN pALANIAPPAN 

GRADUATE  PROJECTS:


Contention Management in Hash-STM

Contention Management is a very important issue in obstruction-free systems as it highly influences the throughput of the system. A variety of contention managers have been proposed for the DSTM system which resolve conflicts based on some heuristics. In this paper, we have evaluated the above schemes in the context of Hash-STM. We have also analyzed the effect of adding read-visibility to Hash-STM and have inferred that the drawbacks outweigh the potential gains. Experimental results show that the aggressive scheme works really well only at lower contention levels. No one scheme performs really well across all the benchmarks. Further, no one  scheme is the best performer across contention levels and tuning  system parameters for one contention level may affect performance at other contention levels. The main contribution of this paper is the adaptive back-off scheme which performs really well for short transactions while only moderate performance is realized for long transactions.

Performance Directed Energy Management using BOS

One of the major challenges in today's computing world is energy management in portable devices and servers.Power management in portable devices is essential to increase battery life. High end server systems use large clusters of machines that consume enormous amount of power. Previous research has devised both software and hardware techniques for memory energy management but has overlooked the performance of applications in such environments. The result is that some of these techniques slowed down an application by 835%. In this paper, we look at software techniques for memory energy management without compromising on performance. The paper conceives of a new approach called BOS - Ballooning in the OS inspired from the VMware ESX server. The BOS approach consists of a kernel daemon which continuously monitors the accesses to memory chips and disk I/O. Based on the profiled information, the BOS daemon decides about powering down/up chips. Powering down is emulated within the kernel using mechanisms such as page migration and invisible buddy. Results indicate that chips with more number of allocated pages may not always be the most frequently accessed ones. A study has been done analyzing the effect of decreased memory size on disk activity and based on the study, a threshold based policy is proposed which is found to settle in the operating point for a simple application. A single page migration incurs a cost of approximately 13 microseconds and is one of the bottlenecks in the BOS approach.

Analysis of Time Synchronization Systems

Time synchronization in the Internet is one of the critical issues that the networking community has been trying to solve in recent years. Researchers have proposed several solutions to this problem such as the Network Time Protocol. Hardware technology also has progressed at a faster pace to diversify the overall solution set. In this context, GPS receivers are one of the major sources of time that are widely deployed to synchronize local clocks to the UTC reference. Although NTP has been widely accepted as a protocol that can synchronize any remote client to a reference clock, a study shows that 300 stratum-1 clocks were found to be faulty. Recently, the TSC register, which counts the CPU cycles in popular PC architectures, was proposed as the basis of a new software clock which in terms of rate performance was shown to perform as well as more expensive GPS alternatives. Muddled with these recent findings, it is high time that these alternative sources of time are evaluated. In this paper, we try to address the following research questions: Do Network Dynamics have a significant impact on the Time Synchronization protocols ? Do Software Clocks provide good stability and accuracy? Are GPS clocks really stable? How to evaluate different clocks in order to assess their stability and accuracy?

Performance Analysis of Microeconomic Algorithms to Distributed Query Processing.

Many Microeconomic approaches have been proposed to the problem of load balancing in distributed systems. Here we explore two such approaches, viz, one based on the Mariposa model and the other one, based on the Ferguson's approach. We obtained interesting insights into the performance of these two algorithms. It was found that the Ferguson's model performed better load balancing when compared to the Mariposa model. The implementation was done in JAVA.

A Study of Mispredicted Branches Dependent on Load Misses in Continual Flow Pipelines.

Long Memory Latencies is the primary problem confounding computer architects right now. CFP is one of the proposed solutions to this problem. We implemented CFP in simple scalar and explored how Mispredicted Branches dependent on Load Misses affect CFP’s performance. We also analyzed the impact of instruction fetch mechanism on CFP's performance.

UNDERGRADUATE  PROJECTS:

Implementation of the Datagram Congestion Control Protocol (DCCP).

 DCCP is a transport layer protocol that is suited to multimedia and streaming applications. It provides an abstract framework within which users can embed custom congestion control algorithms based on their needs. We developed a new congestion control algorithm based on the class of Binomial congestion Control Algorithms and integrated it within the DCCP framework. The entire protocol was implemented in ns2.

Implementation of an Indirect Branch Prediction Technique in Simple Scalar.

A branch prediction technique for indirect branches based on an "XOR" scheme was implemented in simple scalar. We got an improvement of ~3% over the conventional Branch Target Buffer Technique.

Designed a Compiler for a subset of the ICON Language.

ICON is a declarative language like C/Pascal with support for string operations and dynamic typing. Lex was used to construct the Lexical Analyzer while Yacc was used to build the Syntax Directed Translator. The Target Language was 8086 assembly.

Object Oriented Design for a website using IBM-Rational Rose.

The complete design of the website was done in UML (using IBM Rational Rose ) and the final implementation was done in  Java.

Simulated Main Memory and Cache Access in VHDL.

Designed a Digital Stop Clock in Digital Systems Course  ( Hardware Project ).

Developed a Client Server Application using 8086 assembly.

 

 

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