FastSim -- Memoizing Micro-Architecture Simulation

Doctoral research by Eric Schnarr (
at the University of Wisconsin-Madison

Processor simulation, an essential part of micro-architecture research and development, is increasingly slow due to the increased complexity of processor designs. Memoization (an optimization commonly used with functional programming languages) can greatly accelerate complex micro-architecture simulation. For example, FastSim v.1 simulates a detailed out-of-order micro-architecture using memoization, and runs an order of magnitude faster than contemporary out-of-order simulators.

This has been the thesis of my doctoral work at the University of Wisconsin-Madison. A PDF copy of my dissertation can be downloaded from here. This work includes:

Follow one of the links above to learn more about FastSim v.1, v.2, or Facile. A snapshot of the FastSim v.2 source code is available for download here.

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