elastic_trace.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2013 - 2015 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Radhika Jagtap
 *          Andreas Hansson
 *          Thomas Grass
 */

#ifndef __CPU_O3_PROBE_ELASTIC_TRACE_HH__
#define __CPU_O3_PROBE_ELASTIC_TRACE_HH__

#include <set>
#include <unordered_map>
#include <utility>

#include "cpu/o3/dyn_inst.hh"
#include "cpu/o3/impl.hh"
#include "mem/request.hh"
#include "params/ElasticTrace.hh"
#include "proto/inst_dep_record.pb.h"
#include "proto/packet.pb.h"
#include "proto/protoio.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"

class ElasticTrace : public ProbeListenerObject
{

  public:
    typedef typename O3CPUImpl::DynInstPtr DynInstPtr;
    typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair;

    typedef ProtoMessage::InstDepRecord::RecordType RecordType;
    typedef ProtoMessage::InstDepRecord Record;

    ElasticTrace(const ElasticTraceParams *params);

    void regProbeListeners();

    void regEtraceListeners();

    const std::string name() const;

    void flushTraces();

    void fetchReqTrace(const RequestPtr &req);

    void recordExecTick(const DynInstPtr &dyn_inst);

    void recordToCommTick(const DynInstPtr &dyn_inst);

    void updateRegDep(const DynInstPtr &dyn_inst);

    void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);

    void addSquashedInst(const DynInstPtr &head_inst);

    void addCommittedInst(const DynInstPtr &head_inst);

    void regStats();

    EventWrapper<ElasticTrace,
                 &ElasticTrace::regEtraceListeners> regEtraceListenersEvent;

  private:
    bool firstWin;

    struct InstExecInfo
    {
        Tick executeTick;
        Tick toCommitTick;
        std::set<InstSeqNum> physRegDepSet;
        InstExecInfo()
          : executeTick(MaxTick),
            toCommitTick(MaxTick)
        { }
    };

    std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;

    InstSeqNum lastClearedSeqNum;

    std::unordered_map<PhysRegIndex, InstSeqNum> physRegDepMap;

    struct TraceInfo
    {
        /* Instruction sequence number. */
        InstSeqNum instNum;
        RecordType type;
        /* Tick when instruction was in execute stage. */
        Tick executeTick;
        /* Tick when instruction was marked ready and sent to commit stage. */
        Tick toCommitTick;
        /* Tick when instruction was committed. */
        Tick commitTick;
        /* If instruction was committed, as against squashed. */
        bool commit;
        /* List of order dependencies. */
        std::list<InstSeqNum> robDepList;
        /* List of physical register RAW dependencies. */
        std::list<InstSeqNum> physRegDepList;
        int64_t compDelay;
        /* Number of dependents. */
        uint32_t numDepts;
        /* The instruction PC for a load, store or non load/store. */
        Addr pc;
        /* Request flags in case of a load/store instruction */
        Request::FlagsType reqFlags;
        /* Request physical address in case of a load/store instruction */
        Addr physAddr;
        /* Request virtual address in case of a load/store instruction */
        Addr virtAddr;
        /* Address space id in case of a load/store instruction */
        uint32_t asid;
        /* Request size in case of a load/store instruction */
        unsigned size;
        TraceInfo()
          : type(Record::INVALID)
        { }
        bool isLoad() const { return (type == Record::LOAD); }
        bool isStore() const { return (type == Record::STORE); }
        bool isComp() const { return (type == Record::COMP); }
        const std::string& typeToStr() const;
        Tick getExecuteTick() const;
    };

    std::vector<TraceInfo*> depTrace;

    std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;

    typedef typename std::vector<TraceInfo*>::iterator depTraceItr;

    typedef typename std::reverse_iterator<depTraceItr> depTraceRevItr;

    uint32_t depWindowSize;

    ProtoOutputStream* dataTraceStream;

    ProtoOutputStream* instTraceStream;

    const InstSeqNum startTraceInst;

    bool allProbesReg;

    const bool traceVirtAddr;

    FullO3CPU<O3CPUImpl>* cpu;

    void addDepTraceRecord(const DynInstPtr &head_inst,
                           InstExecInfo* exec_info_ptr, bool commit);

    void clearTempStoreUntil(const DynInstPtr head_inst);

    void compDelayRob(TraceInfo* past_record, TraceInfo* new_record);

    void compDelayPhysRegDep(TraceInfo* past_record, TraceInfo* new_record);

    void writeDepTrace(uint32_t num_to_write);

    void updateCommitOrderDep(TraceInfo* new_record, bool find_load_not_store);

    void updateIssueOrderDep(TraceInfo* new_record);

    void assignRobDep(TraceInfo* past_record, TraceInfo* new_record);

    bool hasStoreCommitted(TraceInfo* past_record, Tick execute_tick) const;

    bool hasLoadCompleted(TraceInfo* past_record, Tick execute_tick) const;

    bool hasLoadBeenSent(TraceInfo* past_record, Tick execute_tick) const;

    bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;

    Stats::Scalar numRegDep;

    Stats::Scalar numOrderDepStores;

    Stats::Scalar numIssueOrderDepLoads;

    Stats::Scalar numIssueOrderDepStores;

    Stats::Scalar numIssueOrderDepOther;

    Stats::Scalar numFilteredNodes;

    Stats::Scalar maxNumDependents;

    Stats::Scalar maxTempStoreSize;

    Stats::Scalar maxPhysRegDepMapSize;

};
#endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__