request.hh

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/*
 * Copyright (c) 2012-2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Ron Dreslinski
 *          Steve Reinhardt
 *          Ali Saidi
 */

#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__

#include <cassert>
#include <climits>

#include "base/flags.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "sim/core.hh"

namespace ContextSwitchTaskId {
    enum TaskId {
        MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
        Prefetcher = 1022, /* For cache lines brought in by prefetcher */
        DMA = 1023, /* Mostly Table Walker */
        Unknown = 1024,
        NumTaskId
    };
}

class Request;

typedef Request* RequestPtr;
typedef uint16_t MasterID;

class Request
{
  public:
    typedef uint32_t FlagsType;
    typedef uint8_t ArchFlagsType;
    typedef ::Flags<FlagsType> Flags;

    enum : FlagsType {
        ARCH_BITS                   = 0x000000FF,
        INST_FETCH                  = 0x00000100,
        PHYSICAL                    = 0x00000200,
        UNCACHEABLE                = 0x00000400,
        STRICT_ORDER                = 0x00000800,
        MMAPPED_IPR                 = 0x00002000,
        PRIVILEGED                  = 0x00008000,

        CACHE_BLOCK_ZERO            = 0x00010000,

        NO_ACCESS                   = 0x00080000,
        LOCKED_RMW                  = 0x00100000,
        LLSC                        = 0x00200000,
        MEM_SWAP                    = 0x00400000,
        MEM_SWAP_COND               = 0x00800000,

        PREFETCH                    = 0x01000000,
        PF_EXCLUSIVE                = 0x02000000,
        EVICT_NEXT                  = 0x04000000,
        ACQUIRE                     = 0x00020000,
        RELEASE                     = 0x00040000,

        ATOMIC_RETURN_OP            = 0x40000000,
        ATOMIC_NO_RETURN_OP         = 0x80000000,

        KERNEL                      = 0x00001000,

        GENERIC_IPR                 = 0x08000000,

        SECURE                      = 0x10000000,
        PT_WALK                     = 0x20000000,

        STICKY_FLAGS = INST_FETCH
    };

    enum : MasterID {
        wbMasterId = 0,
        funcMasterId = 1,
        intMasterId = 2,
        invldMasterId = std::numeric_limits<MasterID>::max()
    };
    typedef uint32_t MemSpaceConfigFlagsType;
    typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;

    enum : MemSpaceConfigFlagsType {
        SCOPE_VALID            = 0x00000001,
        WAVEFRONT_SCOPE        = 0x00000002,
        WORKGROUP_SCOPE        = 0x00000004,
        DEVICE_SCOPE           = 0x00000008,
        SYSTEM_SCOPE           = 0x00000010,

        GLOBAL_SEGMENT         = 0x00000020,
        GROUP_SEGMENT          = 0x00000040,
        PRIVATE_SEGMENT        = 0x00000080,
        KERNARG_SEGMENT        = 0x00000100,
        READONLY_SEGMENT       = 0x00000200,
        SPILL_SEGMENT          = 0x00000400,
        ARG_SEGMENT            = 0x00000800,
    };

  private:
    typedef uint8_t PrivateFlagsType;
    typedef ::Flags<PrivateFlagsType> PrivateFlags;

    enum : PrivateFlagsType {
        VALID_SIZE           = 0x00000001,
        VALID_PADDR          = 0x00000002,
        VALID_VADDR          = 0x00000004,
        VALID_INST_SEQ_NUM   = 0x00000008,
        VALID_PC             = 0x00000010,
        VALID_CONTEXT_ID     = 0x00000020,
        VALID_EXTRA_DATA     = 0x00000080,
        STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
    };

  private:

    void
    setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
    {
        _paddr = paddr;
        _size = size;
        _time = time;
        _masterId = mid;
        _flags.clear(~STICKY_FLAGS);
        _flags.set(flags);
        privateFlags.clear(~STICKY_PRIVATE_FLAGS);
        privateFlags.set(VALID_PADDR|VALID_SIZE);
        depth = 0;
        accessDelta = 0;
        //translateDelta = 0;
    }

    Addr _paddr;

    unsigned _size;

    MasterID _masterId;

    Flags _flags;

    MemSpaceConfigFlags _memSpaceConfigFlags;

    PrivateFlags privateFlags;

    Tick _time;

    uint32_t _taskId;

    int _asid;

    Addr _vaddr;

    uint64_t _extraData;

    ContextID _contextId;

    Addr _pc;

    InstSeqNum _reqInstSeqNum;

    AtomicOpFunctor *atomicOpFunctor;

  public:

    Request()
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(0),
          _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {}

    Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
            InstSeqNum seq_num, ContextID cid)
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(0),
          _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {
        setPhys(paddr, size, flags, mid, curTick());
        setContext(cid);
        privateFlags.set(VALID_INST_SEQ_NUM);
    }

    Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(0),
          _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {
        setPhys(paddr, size, flags, mid, curTick());
    }

    Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(0),
          _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {
        setPhys(paddr, size, flags, mid, time);
    }

    Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
            Addr pc)
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(pc),
          _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {
        setPhys(paddr, size, flags, mid, time);
        privateFlags.set(VALID_PC);
    }

    Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
            Addr pc, ContextID cid)
        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
          _extraData(0), _contextId(0), _pc(0),
          _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
          accessDelta(0), depth(0)
    {
        setVirt(asid, vaddr, size, flags, mid, pc);
        setContext(cid);
    }

    Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
            Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
        : atomicOpFunctor(atomic_op)
    {
        setVirt(asid, vaddr, size, flags, mid, pc);
        setContext(cid);
    }

    ~Request()
    {
        if (hasAtomicOpFunctor()) {
            delete atomicOpFunctor;
        }
    }

    void
    setContext(ContextID context_id)
    {
        _contextId = context_id;
        privateFlags.set(VALID_CONTEXT_ID);
    }

    void
    setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
            Addr pc)
    {
        _asid = asid;
        _vaddr = vaddr;
        _size = size;
        _masterId = mid;
        _pc = pc;
        _time = curTick();

        _flags.clear(~STICKY_FLAGS);
        _flags.set(flags);
        privateFlags.clear(~STICKY_PRIVATE_FLAGS);
        privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
        depth = 0;
        accessDelta = 0;
        translateDelta = 0;
    }

    void
    setPaddr(Addr paddr)
    {
        _paddr = paddr;
        privateFlags.set(VALID_PADDR);
    }

    void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
    {
        assert(privateFlags.isSet(VALID_VADDR));
        assert(privateFlags.noneSet(VALID_PADDR));
        assert(split_addr > _vaddr && split_addr < _vaddr + _size);
        req1 = new Request(*this);
        req2 = new Request(*this);
        req1->_size = split_addr - _vaddr;
        req2->_vaddr = split_addr;
        req2->_size = _size - req1->_size;
    }

    bool
    hasPaddr() const
    {
        return privateFlags.isSet(VALID_PADDR);
    }

    Addr
    getPaddr() const
    {
        assert(privateFlags.isSet(VALID_PADDR));
        return _paddr;
    }

    Tick translateDelta;

    Tick accessDelta;

    mutable int depth;

    bool
    hasSize() const
    {
        return privateFlags.isSet(VALID_SIZE);
    }

    unsigned
    getSize() const
    {
        assert(privateFlags.isSet(VALID_SIZE));
        return _size;
    }

    Tick
    time() const
    {
        assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
        return _time;
    }

    bool
    hasAtomicOpFunctor()
    {
        return atomicOpFunctor != NULL;
    }

    AtomicOpFunctor *
    getAtomicOpFunctor()
    {
        assert(atomicOpFunctor != NULL);
        return atomicOpFunctor;
    }

    Flags
    getFlags()
    {
        assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
        return _flags;
    }

    void
    setFlags(Flags flags)
    {
        assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
        _flags.set(flags);
    }

    void
    setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
    {
        assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
        _memSpaceConfigFlags.set(extraFlags);
    }

    bool
    hasVaddr() const
    {
        return privateFlags.isSet(VALID_VADDR);
    }

    Addr
    getVaddr() const
    {
        assert(privateFlags.isSet(VALID_VADDR));
        return _vaddr;
    }

    MasterID
    masterId() const
    {
        return _masterId;
    }

    uint32_t
    taskId() const
    {
        return _taskId;
    }

    void
    taskId(uint32_t id) {
        _taskId = id;
    }

    int
    getAsid() const
    {
        assert(privateFlags.isSet(VALID_VADDR));
        return _asid;
    }

    void
    setAsid(int asid)
    {
        _asid = asid;
    }

    ArchFlagsType
    getArchFlags() const
    {
        assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
        return _flags & ARCH_BITS;
    }

    bool
    extraDataValid() const
    {
        return privateFlags.isSet(VALID_EXTRA_DATA);
    }

    uint64_t
    getExtraData() const
    {
        assert(privateFlags.isSet(VALID_EXTRA_DATA));
        return _extraData;
    }

    void
    setExtraData(uint64_t extraData)
    {
        _extraData = extraData;
        privateFlags.set(VALID_EXTRA_DATA);
    }

    bool
    hasContextId() const
    {
        return privateFlags.isSet(VALID_CONTEXT_ID);
    }

    ContextID
    contextId() const
    {
        assert(privateFlags.isSet(VALID_CONTEXT_ID));
        return _contextId;
    }

    void
    setPC(Addr pc)
    {
        privateFlags.set(VALID_PC);
        _pc = pc;
    }

    bool
    hasPC() const
    {
        return privateFlags.isSet(VALID_PC);
    }

    Addr
    getPC() const
    {
        assert(privateFlags.isSet(VALID_PC));
        return _pc;
    }

    void incAccessDepth() const { depth++; }
    int getAccessDepth() const { return depth; }

    void setTranslateLatency() { translateDelta = curTick() - _time; }
    Tick getTranslateLatency() const { return translateDelta; }

    void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
    Tick getAccessLatency() const { return accessDelta; }

    bool
    hasInstSeqNum() const
    {
        return privateFlags.isSet(VALID_INST_SEQ_NUM);
    }

    InstSeqNum
    getReqInstSeqNum() const
    {
        assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
        return _reqInstSeqNum;
    }

    void
    setReqInstSeqNum(const InstSeqNum seq_num)
    {
        privateFlags.set(VALID_INST_SEQ_NUM);
        _reqInstSeqNum = seq_num;
    }

    bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
    bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
    bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
    bool isPrefetch() const { return _flags.isSet(PREFETCH); }
    bool isLLSC() const { return _flags.isSet(LLSC); }
    bool isPriv() const { return _flags.isSet(PRIVILEGED); }
    bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
    bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
    bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
    bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
    bool isSecure() const { return _flags.isSet(SECURE); }
    bool isPTWalk() const { return _flags.isSet(PT_WALK); }
    bool isAcquire() const { return _flags.isSet(ACQUIRE); }
    bool isRelease() const { return _flags.isSet(RELEASE); }
    bool isKernel() const { return _flags.isSet(KERNEL); }
    bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
    bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }

    bool
    isAtomic() const
    {
        return _flags.isSet(ATOMIC_RETURN_OP) ||
               _flags.isSet(ATOMIC_NO_RETURN_OP);
    }

    bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }

    bool
    isWavefrontScope() const
    {
        assert(isScoped());
        return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
    }

    bool
    isWorkgroupScope() const
    {
        assert(isScoped());
        return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
    }

    bool
    isDeviceScope() const
    {
        assert(isScoped());
        return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
    }

    bool
    isSystemScope() const
    {
        assert(isScoped());
        return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
    }

    bool
    isGlobalSegment() const
    {
        return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
               (!isGroupSegment() && !isPrivateSegment() &&
                !isKernargSegment() && !isReadonlySegment() &&
                !isSpillSegment() && !isArgSegment());
    }

    bool
    isGroupSegment() const
    {
        return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
    }

    bool
    isPrivateSegment() const
    {
        return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
    }

    bool
    isKernargSegment() const
    {
        return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
    }

    bool
    isReadonlySegment() const
    {
        return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
    }

    bool
    isSpillSegment() const
    {
        return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
    }

    bool
    isArgSegment() const
    {
        return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
    }
};

#endif // __MEM_REQUEST_HH__