insttracer.hh

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/*
 * Copyright (c) 2014 ARM Limited
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 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * Authors: Steve Reinhardt
 *          Nathan Binkert
 */

#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__

#include "base/bigint.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"

class ThreadContext;

namespace Trace {

class InstRecord
{
  protected:
    Tick when;

    // The following fields are initialized by the constructor and
    // thus guaranteed to be valid.
    ThreadContext *thread;
    // need to make this ref-counted so it doesn't go away before we
    // dump the record
    StaticInstPtr staticInst;
    TheISA::PCState pc;
    StaticInstPtr macroStaticInst;

    // The remaining fields are only valid for particular instruction
    // types (e.g, addresses for memory ops) or when particular
    // options are enabled (e.g., tracing full register contents).
    // Each data field has an associated valid flag to indicate
    // whether the data field is valid.

    /*** @defgroup mem
     * @{
     * Memory request information in the instruction accessed memory.
     * @see mem_valid
     */
    Addr addr; 
    Addr size; 
    unsigned flags; 

    union {
        uint64_t as_int;
        double as_double;
    } data;

    InstSeqNum fetch_seq;

    InstSeqNum cp_seq;

    enum {
        DataInvalid = 0,
        DataInt8 = 1,   // set to equal number of bytes
        DataInt16 = 2,
        DataInt32 = 4,
        DataInt64 = 8,
        DataDouble = 3
    } data_status;

    bool mem_valid;

    bool fetch_seq_valid;
    bool cp_seq_valid;

    bool predicate;

  public:
    InstRecord(Tick _when, ThreadContext *_thread,
               const StaticInstPtr _staticInst,
               TheISA::PCState _pc,
               const StaticInstPtr _macroStaticInst = NULL)
        : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
        macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
        fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
        fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
    { }

    virtual ~InstRecord() { }

    void setWhen(Tick new_when) { when = new_when; }
    void setMem(Addr a, Addr s, unsigned f)
    {
        addr = a; size = s; flags = f; mem_valid = true;
    }

    void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
    void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }

    void setData(int64_t d) { setData((uint64_t)d); }
    void setData(int32_t d) { setData((uint32_t)d); }
    void setData(int16_t d) { setData((uint16_t)d); }
    void setData(int8_t d)  { setData((uint8_t)d); }

    void setData(double d) { data.as_double = d; data_status = DataDouble; }

    void setFetchSeq(InstSeqNum seq)
    { fetch_seq = seq; fetch_seq_valid = true; }

    void setCPSeq(InstSeqNum seq)
    { cp_seq = seq; cp_seq_valid = true; }

    void setPredicate(bool val) { predicate = val; }

    virtual void dump() = 0;

  public:
    Tick getWhen() const { return when; }
    ThreadContext *getThread() const { return thread; }
    StaticInstPtr getStaticInst() const { return staticInst; }
    TheISA::PCState getPCState() const { return pc; }
    StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }

    Addr getAddr() const { return addr; }
    Addr getSize() const { return size; }
    unsigned getFlags() const { return flags; }
    bool getMemValid() const { return mem_valid; }

    uint64_t getIntData() const { return data.as_int; }
    double getFloatData() const { return data.as_double; }
    int getDataStatus() const { return data_status; }

    InstSeqNum getFetchSeq() const { return fetch_seq; }
    bool getFetchSeqValid() const { return fetch_seq_valid; }

    InstSeqNum getCpSeq() const { return cp_seq; }
    bool getCpSeqValid() const { return cp_seq_valid; }
};

class InstTracer : public SimObject
{
  public:
    InstTracer(const Params *p) : SimObject(p)
    {}

    virtual ~InstTracer()
    {};

    virtual InstRecord *
        getInstRecord(Tick when, ThreadContext *tc,
                const StaticInstPtr staticInst, TheISA::PCState pc,
                const StaticInstPtr macroStaticInst = NULL) = 0;
};



} // namespace Trace

#endif // __INSTRECORD_HH__