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cpu.hh
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39 
46 #ifndef __CPU_MINOR_CPU_HH__
47 #define __CPU_MINOR_CPU_HH__
48 
49 #include "cpu/minor/activity.hh"
50 #include "cpu/minor/stats.hh"
51 #include "cpu/base.hh"
52 #include "cpu/simple_thread.hh"
53 #include "enums/ThreadPolicy.hh"
54 #include "params/MinorCPU.hh"
55 
56 namespace Minor
57 {
60 class Pipeline;
61 
64 };
65 
79 class MinorCPU : public BaseCPU
80 {
81  protected:
85 
86  public:
91 
96 
97  public:
100  class MinorCPUPort : public MasterPort
101  {
102  public:
105 
106  public:
107  MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
108  : MasterPort(name_, &cpu_), cpu(cpu_)
109  { }
110 
111  };
112 
114  Enums::ThreadPolicy threadPolicy;
115  protected:
117  MasterPort &getDataPort() override;
118 
120  MasterPort &getInstPort() override;
121 
122  public:
123  MinorCPU(MinorCPUParams *params);
124 
125  ~MinorCPU();
126 
127  public:
129  void init() override;
130  void startup() override;
131  void wakeup(ThreadID tid) override;
132 
134 
137 
139  void regStats() override;
140 
142  Counter totalInsts() const override;
143  Counter totalOps() const override;
144 
145  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
146  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
147 
149  void serialize(CheckpointOut &cp) const override;
150  void unserialize(CheckpointIn &cp) override;
151 
153  DrainState drain() override;
154  void drainResume() override;
157  void signalDrainDone();
158  void memWriteback() override;
159 
161  void switchOut() override;
162  void takeOverFrom(BaseCPU *old_cpu) override;
163 
165  void activateContext(ThreadID thread_id) override;
166  void suspendContext(ThreadID thread_id) override;
167 
170  {
171  std::vector<ThreadID> prio_list;
172  for (ThreadID i = 1; i <= numThreads; i++) {
173  prio_list.push_back((priority + i) % numThreads);
174  }
175  return prio_list;
176  }
177 
179  {
180  std::vector<ThreadID> prio_list;
181  for (ThreadID i = 0; i < numThreads; i++) {
182  prio_list.push_back(i);
183  }
184  std::random_shuffle(prio_list.begin(), prio_list.end());
185  return prio_list;
186  }
187 
192  void wakeupOnEvent(unsigned int stage_id);
193 };
194 
195 #endif /* __CPU_MINOR_CPU_HH__ */
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:167
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
Definition: cpu.cc:217
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:104
The stats for MinorCPU separated from the CPU definition.
Bitfield< 7 > i
Definition: miscregs.hh:1378
DrainState
Object drain/handover states.
Definition: drain.hh:71
Counter totalOps() const override
Definition: cpu.cc:342
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:305
MasterPort & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:320
void startup() override
Definition: cpu.cc:180
ip6_addr_t addr
Definition: inet.hh:335
ActivityRecoder from cpu/activity.h wrapped to provide evaluate and minorTrace.
ActivityRecorder with a Ticked interface.
Definition: activity.hh:56
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:84
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:107
void drainResume() override
Definition: cpu.cc:224
DrainState drain() override
Drain interface.
Definition: cpu.cc:196
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:100
void unserialize(CheckpointIn &cp) override
Definition: cpu.cc:153
Addr dbg_vtophys(Addr addr)
Definition: cpu.cc:160
MasterPort & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:325
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:94
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:140
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:146
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:60
std::vector< ThreadID > randomPriority()
Definition: cpu.hh:178
void memWriteback() override
Definition: cpu.cc:250
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:90
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
int64_t Counter
Statistics counter type.
Definition: types.hh:58
void takeOverFrom(BaseCPU *old_cpu) override
Definition: cpu.cc:268
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition: cpu.hh:169
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
MinorCPU(MinorCPUParams *params)
Definition: cpu.cc:50
Enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition: cpu.hh:114
std::ostream CheckpointOut
Definition: serialize.hh:67
void suspendContext(ThreadID thread_id) override
Definition: cpu.cc:295
void wakeup(ThreadID tid) override
Definition: cpu.cc:169
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:95
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
Minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:136
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:276
The constructed pipeline.
Definition: pipeline.hh:71
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:134
Currently unused stats class.
Definition: stats.hh:57
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:256
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:126
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:331
~MinorCPU()
Definition: cpu.cc:84

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