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cpu.cc
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36  *
37  * Authors: Andrew Bardsley
38  */
39 
40 #include "cpu/minor/cpu.hh"
41 
42 #include "arch/utility.hh"
43 #include "cpu/minor/dyn_inst.hh"
44 #include "cpu/minor/fetch1.hh"
45 #include "cpu/minor/pipeline.hh"
46 #include "debug/Drain.hh"
47 #include "debug/MinorCPU.hh"
48 #include "debug/Quiesce.hh"
49 
50 MinorCPU::MinorCPU(MinorCPUParams *params) :
51  BaseCPU(params),
52  threadPolicy(params->threadPolicy)
53 {
54  /* This is only written for one thread at the moment */
55  Minor::MinorThread *thread;
56 
57  for (ThreadID i = 0; i < numThreads; i++) {
58  if (FullSystem) {
59  thread = new Minor::MinorThread(this, i, params->system,
60  params->itb, params->dtb, params->isa[i]);
62  } else {
63  thread = new Minor::MinorThread(this, i, params->system,
64  params->workload[i], params->itb, params->dtb,
65  params->isa[i]);
66  }
67 
68  threads.push_back(thread);
69  ThreadContext *tc = thread->getTC();
70  threadContexts.push_back(tc);
71  }
72 
73 
74  if (params->checker) {
75  fatal("The Minor model doesn't support checking (yet)\n");
76  }
77 
79 
80  pipeline = new Minor::Pipeline(*this, *params);
82 }
83 
85 {
86  delete pipeline;
87 
88  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
89  delete threads[thread_id];
90  }
91 }
92 
93 void
95 {
96  BaseCPU::init();
97 
98  if (!params()->switched_out &&
99  system->getMemoryMode() != Enums::timing)
100  {
101  fatal("The Minor CPU requires the memory system to be in "
102  "'timing' mode.\n");
103  }
104 
105  /* Initialise the ThreadContext's memory proxies */
106  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
107  ThreadContext *tc = getContext(thread_id);
108 
109  tc->initMemProxies(tc);
110  }
111 
112  /* Initialise CPUs (== threads in the ISA) */
113  if (FullSystem && !params()->switched_out) {
114  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++)
115  {
116  ThreadContext *tc = getContext(thread_id);
117 
118  /* Initialize CPU, including PC */
119  TheISA::initCPU(tc, cpuId());
120  }
121  }
122 }
123 
125 void
127 {
128  BaseCPU::regStats();
129  stats.regStats(name(), *this);
130  pipeline->regStats();
131 }
132 
133 void
135 {
136  threads[thread_id]->serialize(cp);
137 }
138 
139 void
141 {
142  threads[thread_id]->unserialize(cp);
143 }
144 
145 void
147 {
148  pipeline->serialize(cp);
149  BaseCPU::serialize(cp);
150 }
151 
152 void
154 {
155  pipeline->unserialize(cp);
157 }
158 
159 Addr
161 {
162  /* Note that this gives you the translation for thread 0 */
163  panic("No implementation for vtophy\n");
164 
165  return 0;
166 }
167 
168 void
170 {
171  DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
172  assert(tid < numThreads);
173 
174  if (threads[tid]->status() == ThreadContext::Suspended) {
175  threads[tid]->activate();
176  }
177 }
178 
179 void
181 {
182  DPRINTF(MinorCPU, "MinorCPU startup\n");
183 
184  BaseCPU::startup();
185 
186  for (auto i = threads.begin(); i != threads.end(); i ++)
187  (*i)->startup();
188 
189  for (ThreadID tid = 0; tid < numThreads; tid++) {
190  threads[tid]->startup();
191  pipeline->wakeupFetch(tid);
192  }
193 }
194 
197 {
198  if (switchedOut()) {
199  DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
200  return DrainState::Drained;
201  }
202 
203  DPRINTF(Drain, "MinorCPU drain\n");
204 
205  /* Need to suspend all threads and wait for Execute to idle.
206  * Tell Fetch1 not to fetch */
207  if (pipeline->drain()) {
208  DPRINTF(Drain, "MinorCPU drained\n");
209  return DrainState::Drained;
210  } else {
211  DPRINTF(Drain, "MinorCPU not finished draining\n");
212  return DrainState::Draining;
213  }
214 }
215 
216 void
218 {
219  DPRINTF(Drain, "MinorCPU drain done\n");
221 }
222 
223 void
225 {
226  /* When taking over from another cpu make sure lastStopped
227  * is reset since it might have not been defined previously
228  * and might lead to a stats corruption */
230 
231  if (switchedOut()) {
232  DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
233  return;
234  }
235 
236  DPRINTF(Drain, "MinorCPU drainResume\n");
237 
238  if (!system->isTimingMode()) {
239  fatal("The Minor CPU requires the memory system to be in "
240  "'timing' mode.\n");
241  }
242 
243  for (ThreadID tid = 0; tid < numThreads; tid++)
244  wakeup(tid);
245 
247 }
248 
249 void
251 {
252  DPRINTF(Drain, "MinorCPU memWriteback\n");
253 }
254 
255 void
257 {
258  DPRINTF(MinorCPU, "MinorCPU switchOut\n");
259 
260  assert(!switchedOut());
261  BaseCPU::switchOut();
262 
263  /* Check that the CPU is drained? */
265 }
266 
267 void
269 {
270  DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
271 
272  BaseCPU::takeOverFrom(old_cpu);
273 }
274 
275 void
277 {
278  DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
279 
280  /* Do some cycle accounting. lastStopped is reset to stop the
281  * wakeup call on the pipeline from adding the quiesce period
282  * to BaseCPU::numCycles */
285 
286  /* Wake up the thread, wakeup the pipeline tick */
287  threads[thread_id]->activate();
289  pipeline->wakeupFetch(thread_id);
290 
291  BaseCPU::activateContext(thread_id);
292 }
293 
294 void
296 {
297  DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
298 
299  threads[thread_id]->suspend();
300 
301  BaseCPU::suspendContext(thread_id);
302 }
303 
304 void
305 MinorCPU::wakeupOnEvent(unsigned int stage_id)
306 {
307  DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
308 
309  /* Mark that some activity has taken place and start the pipeline */
310  activityRecorder->activateStage(stage_id);
311  pipeline->start();
312 }
313 
314 MinorCPU *
315 MinorCPUParams::create()
316 {
317  return new MinorCPU(this);
318 }
319 
321 {
322  return pipeline->getInstPort();
323 }
324 
326 {
327  return pipeline->getDataPort();
328 }
329 
330 Counter
332 {
333  Counter ret = 0;
334 
335  for (auto i = threads.begin(); i != threads.end(); i ++)
336  ret += (*i)->numInst;
337 
338  return ret;
339 }
340 
341 Counter
343 {
344  Counter ret = 0;
345 
346  for (auto i = threads.begin(); i != threads.end(); i ++)
347  ret += (*i)->numOp;
348 
349  return ret;
350 }
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:167
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
Definition: cpu.cc:217
#define DPRINTF(x,...)
Definition: trace.hh:212
void drainResume()
Definition: pipeline.cc:213
void regStats(const std::string &name, BaseCPU &baseCpu)
Definition: stats.cc:49
Top level definition of the Minor in-order CPU model.
Stats::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition: stats.hh:73
const std::string & name()
Definition: trace.cc:49
Bitfield< 7 > i
Definition: miscregs.hh:1378
DrainState
Object drain/handover states.
Definition: drain.hh:71
#define panic(...)
Definition: misc.hh:153
void resetLastStopped()
Reset stopped time to current time.
void setStatus(Status newStatus)
Running normally.
Counter totalOps() const override
Definition: cpu.cc:342
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:305
MasterPort & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:320
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void startup() override
Definition: cpu.cc:180
ip6_addr_t addr
Definition: inet.hh:335
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:146
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
MinorCPU::MinorCPUPort & getInstPort()
Functions below here are BaseCPU operations passed on to pipeline stages.
Definition: pipeline.cc:179
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:84
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:126
MinorActivityRecorder * getActivityRecorder()
To give the activity recorder to the CPU.
Definition: pipeline.hh:145
MinorCPU::MinorCPUPort & getDataPort()
Return the DcachePort belonging to Execute for the CPU.
Definition: pipeline.cc:185
void drainResume() override
Definition: cpu.cc:224
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void serialize(CheckpointOut &cp) const override
Checkpoint lastStopped.
DrainState drain() override
Drain interface.
Definition: cpu.cc:196
Bitfield< 5, 0 > status
Definition: miscregs.hh:1604
Cycles cyclesSinceLastStopped() const
How long have we been stopped for?
bool drain()
Try to drain the CPU.
Definition: pipeline.cc:197
void unserialize(CheckpointIn &cp) override
Definition: cpu.cc:153
Addr dbg_vtophys(Addr addr)
Definition: cpu.cc:160
system
Definition: isa.cc:226
MasterPort & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:325
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:94
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void initCPU(ThreadContext *tc, int cpuId)
Definition: ev5.cc:51
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:140
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:146
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:60
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:92
void memWriteback() override
Definition: cpu.cc:250
#define fatal(...)
Definition: misc.hh:163
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:90
static void init()
Initialise the class.
Definition: dyn_inst.cc:81
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
void start()
Start ticking.
Draining buffers pending serialization/handover.
int64_t Counter
Statistics counter type.
Definition: types.hh:58
void takeOverFrom(BaseCPU *old_cpu) override
Definition: cpu.cc:268
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
void wakeupFetch(ThreadID tid)
Wake up the Fetch unit.
Definition: pipeline.cc:191
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
void regStats()
Register {num,ticks}Cycles if necessary.
MinorCPU(MinorCPUParams *params)
Definition: cpu.cc:50
std::ostream CheckpointOut
Definition: serialize.hh:67
Permanently shut down.
void suspendContext(ThreadID thread_id) override
Definition: cpu.cc:295
void wakeup(ThreadID tid) override
Definition: cpu.cc:169
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:95
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:267
The constructed pipeline.
Temporarily inactive.
void serialize(CheckpointOut &cp) const override
void unserialize(CheckpointIn &cp) override
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
Minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:136
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:276
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU...
The constructed pipeline.
Definition: pipeline.hh:71
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:134
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:256
const FlagsType init
This Stat is Initialized.
Definition: info.hh:45
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:126
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:331
~MinorCPU()
Definition: cpu.cc:84

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