thread_context.hh

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/*
 * Copyright (c) 2011-2012 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * to a hardware implementation of the functionality of the software
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 * All rights reserved.
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 * Authors: Kevin Lim
 */

#ifndef __CPU_O3_THREAD_CONTEXT_HH__
#define __CPU_O3_THREAD_CONTEXT_HH__

#include "config/the_isa.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/thread_context.hh"

class EndQuiesceEvent;
namespace Kernel {
    class Statistics;
}

template <class Impl>
class O3ThreadContext : public ThreadContext
{
  public:
    typedef typename Impl::O3CPU O3CPU;

    O3CPU *cpu;

    O3ThreadState<Impl> *thread;

    TheISA::TLB *getITBPtr() { return cpu->itb; }

    TheISA::TLB *getDTBPtr() { return cpu->dtb; }

    CheckerCPU *getCheckerCpuPtr() { return NULL; }

    TheISA::Decoder *
    getDecoderPtr()
    {
        return cpu->fetch.decoder[thread->threadId()];
    }

    virtual BaseCPU *getCpuPtr() { return cpu; }

    virtual int cpuId() const { return cpu->cpuId(); }

    virtual uint32_t socketId() const { return cpu->socketId(); }

    virtual ContextID contextId() const { return thread->contextId(); }

    virtual void setContextId(int id) { thread->setContextId(id); }

    virtual int threadId() const { return thread->threadId(); }
    virtual void setThreadId(int id) { return thread->setThreadId(id); }

    virtual System *getSystemPtr() { return cpu->system; }

    virtual TheISA::Kernel::Statistics *getKernelStats()
    { return thread->kernelStats; }

    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }

    virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); }

    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }

    virtual FSTranslatingPortProxy &getVirtProxy();

    virtual void initMemProxies(ThreadContext *tc)
    { thread->initMemProxies(tc); }

    virtual SETranslatingPortProxy &getMemProxy()
    { return thread->getMemProxy(); }

    virtual Status status() const { return thread->status(); }

    virtual void setStatus(Status new_status)
    { thread->setStatus(new_status); }

    virtual void activate();

    virtual void suspend();

    virtual void halt();

    virtual void dumpFuncProfile();

    virtual void takeOverFrom(ThreadContext *old_context);

    virtual void regStats(const std::string &name);

    virtual Tick readLastActivate();
    virtual Tick readLastSuspend();

    virtual void profileClear();
    virtual void profileSample();

    virtual void copyArchRegs(ThreadContext *tc);

    virtual void clearArchRegs();

    virtual uint64_t readIntReg(int reg_idx) {
        return readIntRegFlat(flattenIntIndex(reg_idx));
    }

    virtual FloatReg readFloatReg(int reg_idx) {
        return readFloatRegFlat(flattenFloatIndex(reg_idx));
    }

    virtual FloatRegBits readFloatRegBits(int reg_idx) {
        return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
    }

    virtual CCReg readCCReg(int reg_idx) {
        return readCCRegFlat(flattenCCIndex(reg_idx));
    }

    virtual void setIntReg(int reg_idx, uint64_t val) {
        setIntRegFlat(flattenIntIndex(reg_idx), val);
    }

    virtual void setFloatReg(int reg_idx, FloatReg val) {
        setFloatRegFlat(flattenFloatIndex(reg_idx), val);
    }

    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
        setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
    }

    virtual void setCCReg(int reg_idx, CCReg val) {
        setCCRegFlat(flattenCCIndex(reg_idx), val);
    }

    virtual TheISA::PCState pcState()
    { return cpu->pcState(thread->threadId()); }

    virtual void pcState(const TheISA::PCState &val);

    virtual void pcStateNoRecord(const TheISA::PCState &val);

    virtual Addr instAddr()
    { return cpu->instAddr(thread->threadId()); }

    virtual Addr nextInstAddr()
    { return cpu->nextInstAddr(thread->threadId()); }

    virtual MicroPC microPC()
    { return cpu->microPC(thread->threadId()); }

    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }

    virtual MiscReg readMiscReg(int misc_reg)
    { return cpu->readMiscReg(misc_reg, thread->threadId()); }

    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);

    virtual void setMiscReg(int misc_reg, const MiscReg &val);

    virtual int flattenIntIndex(int reg);
    virtual int flattenFloatIndex(int reg);
    virtual int flattenCCIndex(int reg);
    virtual int flattenMiscIndex(int reg);

    // @todo: Figure out where these store cond failures should go.
    virtual unsigned readStCondFailures()
    { return thread->storeCondFailures; }

    virtual void setStCondFailures(unsigned sc_failures)
    { thread->storeCondFailures = sc_failures; }

    virtual void syscall(int64_t callnum, Fault *fault)
    { return cpu->syscall(callnum, thread->threadId(), fault); }

    virtual Counter readFuncExeInst() { return thread->funcExeInst; }

    virtual EndQuiesceEvent *getQuiesceEvent()
    {
        return this->thread->quiesceEvent;
    }
    inline void conditionalSquash()
    {
        if (!thread->trapPending && !thread->noSquashFromTC)
            cpu->squashFromTC(thread->threadId());
    }

    virtual uint64_t readIntRegFlat(int idx);
    virtual void setIntRegFlat(int idx, uint64_t val);

    virtual FloatReg readFloatRegFlat(int idx);
    virtual void setFloatRegFlat(int idx, FloatReg val);

    virtual FloatRegBits readFloatRegBitsFlat(int idx);
    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);

    virtual CCReg readCCRegFlat(int idx);
    virtual void setCCRegFlat(int idx, CCReg val);
};

#endif