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decoder.hh
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30 
31 #ifndef __ARCH_POWER_DECODER_HH__
32 #define __ARCH_POWER_DECODER_HH__
33 
35 #include "arch/types.hh"
36 #include "cpu/static_inst.hh"
37 
38 namespace PowerISA
39 {
40 
41 class ISA;
42 class Decoder
43 {
44  protected:
45  // The extended machine instruction being generated
47  bool instDone;
48 
49  public:
50  Decoder(ISA* isa = nullptr) : instDone(false)
51  {
52  }
53 
54  void
56  {
57  }
58 
59  void
61  {
62  instDone = false;
63  }
64 
65  // Use this to give data to the predecoder. This should be used
66  // when there is control flow.
67  void
68  moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
69  {
70  emi = inst;
71  instDone = true;
72  }
73 
74  // Use this to give data to the predecoder. This should be used
75  // when instructions are executed in order.
76  void
77  moreBytes(MachInst machInst)
78  {
79  moreBytes(0, 0, machInst);
80  }
81 
82  bool
84  {
85  return true;
86  }
87 
88  bool
90  {
91  return instDone;
92  }
93 
94  void takeOverFrom(Decoder *old) {}
95 
96  protected:
99 
100  public:
102 
108  {
109  return defaultCache.decode(this, mach_inst, addr);
110  }
111 
114  {
115  if (!instDone)
116  return NULL;
117  instDone = false;
118  return decode(emi, nextPC.instAddr());
119  }
120 };
121 
122 } // namespace PowerISA
123 
124 #endif // __ARCH_POWER_DECODER_HH__
bool instReady()
Definition: decoder.hh:89
StaticInstPtr decodeInst(ExtMachInst mach_inst)
ip6_addr_t addr
Definition: inet.hh:335
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:50
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:107
void takeOverFrom(Decoder *old)
Definition: decoder.hh:94
bool needMoreBytes()
Definition: decoder.hh:83
void process()
Definition: decoder.hh:55
ExtMachInst emi
Definition: decoder.hh:46
uint32_t MachInst
Definition: types.hh:41
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition: decoder.hh:68
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:42
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
uint64_t ExtMachInst
Definition: types.hh:41
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
StaticInstPtr decode(PowerISA::PCState &nextPC)
Definition: decoder.hh:113
IntReg pc
Definition: remote_gdb.hh:91
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:98
void moreBytes(MachInst machInst)
Definition: decoder.hh:77

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