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isa.hh
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1 /*
2  * Copyright (c) 2009 The Regents of The University of Michigan
3  * Copyright (c) 2009 The University of Edinburgh
4  * All rights reserved.
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7  * modification, are permitted provided that the following conditions are
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9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
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13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28  *
29  * Authors: Gabe Black
30  * Timothy M. Jones
31  */
32 
33 #ifndef __ARCH_POWER_ISA_HH__
34 #define __ARCH_POWER_ISA_HH__
35 
36 #include "arch/power/registers.hh"
37 #include "arch/power/types.hh"
38 #include "base/misc.hh"
39 #include "sim/sim_object.hh"
40 
41 struct PowerISAParams;
42 class ThreadContext;
43 class Checkpoint;
44 class EventManager;
45 
46 namespace PowerISA
47 {
48 
49 class ISA : public SimObject
50 {
51  protected:
54 
55  public:
56  typedef PowerISAParams Params;
57 
58  void
60  {
61  }
62 
63  MiscReg
64  readMiscRegNoEffect(int misc_reg) const
65  {
66  fatal("Power does not currently have any misc regs defined\n");
67  return dummy;
68  }
69 
70  MiscReg
71  readMiscReg(int misc_reg, ThreadContext *tc)
72  {
73  fatal("Power does not currently have any misc regs defined\n");
74  return dummy;
75  }
76 
77  void
78  setMiscRegNoEffect(int misc_reg, const MiscReg &val)
79  {
80  fatal("Power does not currently have any misc regs defined\n");
81  }
82 
83  void
84  setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
85  {
86  fatal("Power does not currently have any misc regs defined\n");
87  }
88 
89  int
90  flattenIntIndex(int reg) const
91  {
92  return reg;
93  }
94 
95  int
97  {
98  return reg;
99  }
100 
101  // dummy
102  int
103  flattenCCIndex(int reg) const
104  {
105  return reg;
106  }
107 
108  int
110  {
111  return reg;
112  }
113 
114  void startup(ThreadContext *tc) {}
115 
117  using SimObject::startup;
118 
119  const Params *params() const;
120 
121  ISA(Params *p);
122 };
123 
124 } // namespace PowerISA
125 
126 #endif // __ARCH_POWER_ISA_HH__
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
Definition: isa.hh:84
Bitfield< 5, 3 > reg
Definition: types.hh:89
PowerISAParams Params
Definition: isa.hh:56
MiscReg dummy
Definition: isa.hh:52
void clear()
Definition: isa.hh:59
int flattenIntIndex(int reg) const
Definition: isa.hh:90
void startup(ThreadContext *tc)
Definition: isa.hh:114
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Bitfield< 63 > val
Definition: misc.hh:770
int flattenCCIndex(int reg) const
Definition: isa.hh:103
const int NumMiscRegs
Definition: registers.hh:71
const Params * params() const
Definition: isa.cc:54
#define fatal(...)
Definition: misc.hh:163
MiscReg miscRegs[NumMiscRegs]
Definition: isa.hh:53
int flattenMiscIndex(int reg) const
Definition: isa.hh:109
uint64_t MiscReg
Definition: registers.hh:53
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
Definition: isa.hh:78
int flattenFloatIndex(int reg) const
Definition: isa.hh:96
ISA(Params *p)
Definition: isa.cc:47
MiscReg readMiscRegNoEffect(int misc_reg) const
Definition: isa.hh:64
Bitfield< 0 > p
Abstract superclass for simulation objects.
Definition: sim_object.hh:94
MiscReg readMiscReg(int misc_reg, ThreadContext *tc)
Definition: isa.hh:71
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:97

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